Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.69	100.00	81.76			97.01	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	90.91	100.00	72.73			90.91	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T98
1	1	Covered	T2,T4,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T144,T145

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T144,T145
1	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T144,T145
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T34,T35
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T34,T35

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T6,T34,T35

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T4,T5
1	0	-	Covered	T2,T4,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	6768	6768	0	0
MinimalSramFifoDepth_A	6768	6768	0	0
NoErr_A	1575464500	1574773172	0	0
NoSramReadWhenEmpty_A	1575464500	1247928927	0	0
NoSramWriteWhenFull_A	1575464500	18575130	0	0
OupBufWreadyAfterSramRead_A	1575464500	646444	0	0
SramRvalidAfterRead_A	1575464500	646444	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6768	6768	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6768	6768	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575464500	1574773172	0	0
T1	184084	183820	0	0
T2	129700	129440	0	0
T3	6764	6448	0	0
T4	581844	581572	0	0
T5	76296	74092	0	0
T6	68564	68224	0	0
T7	179732	179440	0	0
T8	387676	387404	0	0
T9	1527588	1527568	0	0
T10	39104	37248	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575464500	1247928927	0	0
T1	184084	138409	0	0
T2	129700	106706	0	0
T3	6764	6448	0	0
T4	581844	501029	0	0
T5	76296	65587	0	0
T6	68564	54198	0	0
T7	179732	136034	0	0
T8	387676	310065	0	0
T9	1527588	1162386	0	0
T10	39104	35906	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575464500	18575130	0	0
T1	46021	1000	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	0	0	0
T6	34282	2280	0	0
T7	89866	0	0	0
T8	193838	0	0	0
T9	763794	0	0	0
T10	19552	0	0	0
T15	0	505412	0	0
T17	0	591	0	0
T18	59699	0	0	0
T21	0	139092	0	0
T28	0	525	0	0
T34	178725	2718	0	0
T37	7836	0	0	0
T46	46846	0	0	0
T48	2369	0	0	0
T50	0	111361	0	0
T51	26542	0	0	0
T52	5802	0	0	0
T53	96095	0	0	0
T57	0	8	0	0
T59	0	1371	0	0
T60	0	13	0	0
T64	98470	0	0	0
T69	0	853	0	0
T70	21619	0	0	0
T80	1639	0	0	0
T146	0	5254	0	0
T147	0	76078	0	0
T148	0	183173	0	0
T149	0	2173	0	0
T150	0	1758	0	0
T151	0	1624	0	0
T152	0	1426	0	0
T153	0	26	0	0
T154	0	8	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575464500	646444	0	0
T2	32425	47	0	0
T3	1691	0	0	0
T4	290922	1	0	0
T5	38148	39	0	0
T6	34282	86	0	0
T7	89866	256	0	0
T8	193838	41	0	0
T9	763794	509	0	0
T10	19552	3	0	0
T18	0	26	0	0
T26	0	2375	0	0
T34	178725	868	0	0
T35	156197	0	0	0
T37	15672	0	0	0
T46	46846	100	0	0
T47	0	39	0	0
T48	2369	0	0	0
T50	180557	275	0	0
T51	26542	35	0	0
T52	5802	2	0	0
T53	96095	248	0	0
T64	0	314	0	0
T65	0	59	0	0
T70	21619	55	0	0
T71	121905	0	0	0
T80	1639	0	0	0
T146	0	89	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575464500	646444	0	0
T2	32425	47	0	0
T3	1691	0	0	0
T4	290922	1	0	0
T5	38148	39	0	0
T6	34282	86	0	0
T7	89866	256	0	0
T8	193838	41	0	0
T9	763794	509	0	0
T10	19552	3	0	0
T18	0	26	0	0
T26	0	2375	0	0
T34	178725	868	0	0
T35	156197	0	0	0
T37	15672	0	0	0
T46	46846	100	0	0
T47	0	39	0	0
T48	2369	0	0	0
T50	180557	275	0	0
T51	26542	35	0	0
T52	5802	2	0	0
T53	96095	248	0	0
T64	0	314	0	0
T65	0	59	0	0
T70	21619	55	0	0
T71	121905	0	0	0
T80	1639	0	0	0
T146	0	89	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T5,T6

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T50,T146
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T50,T146

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Not Covered
1	1	Covered	T6,T50,T146

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T5,T6
1	0	-	Covered	T2,T5,T6
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	393866125	393693293	0	0
NoSramReadWhenEmpty_A	393866125	340125312	0	0
NoSramWriteWhenFull_A	393866125	17962749	0	0
OupBufWreadyAfterSramRead_A	393866125	183466	0	0
SramRvalidAfterRead_A	393866125	183466	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	340125312	0	0
T1	46021	45955	0	0
T2	32425	9626	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	10018	0	0
T6	17141	3030	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	7970	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	17962749	0	0
T6	17141	2280	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T15	0	505412	0	0
T17	0	591	0	0
T18	59699	0	0	0
T21	0	139092	0	0
T28	0	525	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T50	0	111361	0	0
T51	26542	0	0	0
T64	98470	0	0	0
T146	0	5254	0	0
T147	0	76078	0	0
T148	0	183173	0	0
T149	0	2173	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	183466	0	0
T2	32425	47	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	39	0	0
T6	17141	86	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	3	0	0
T18	0	26	0	0
T26	0	1197	0	0
T37	7836	0	0	0
T46	0	100	0	0
T47	0	39	0	0
T50	0	275	0	0
T146	0	89	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	183466	0	0
T2	32425	47	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	39	0	0
T6	17141	86	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	3	0	0
T18	0	26	0	0
T26	0	1197	0	0
T37	7836	0	0	0
T46	0	100	0	0
T47	0	39	0	0
T50	0	275	0	0
T146	0	89	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T51

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T8,T51

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T8,T51

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T8,T51

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T51
0	1	Covered	T4,T8,T51
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T8,T51

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T8,T51
1	0	Covered	T4,T51,T64

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T51,T64

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T8,T51

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T51,T64

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T51
1	1	Covered	T4,T51,T64

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T51
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T51

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T51

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T55,T56
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T54,T55,T56

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T51
1	0	Not Covered
1	1	Covered	T54,T55,T56

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T51
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T8,T51
1	0	-	Covered	T4,T8,T51
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	393866125	393693293	0	0
NoSramReadWhenEmpty_A	393866125	372238155	0	0
NoSramWriteWhenFull_A	393866125	344936	0	0
OupBufWreadyAfterSramRead_A	393866125	110366	0	0
SramRvalidAfterRead_A	393866125	110366	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	372238155	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	64868	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96707	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	344936	0	0
T16	255157	0	0	0
T54	13659	7364	0	0
T55	15049	11349	0	0
T56	0	8452	0	0
T155	0	7179	0	0
T156	0	9774	0	0
T157	0	4018	0	0
T158	0	9164	0	0
T159	0	8455	0	0
T160	0	5389	0	0
T161	0	7727	0	0
T162	1543	0	0	0
T163	32770	0	0	0
T164	1515	0	0	0
T165	10496	0	0	0
T166	50788	0	0	0
T167	52383	0	0	0
T168	79489	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	110366	0	0
T4	145461	207	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	1	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	71	0	0
T53	0	110	0	0
T64	0	153	0	0
T65	0	87	0	0
T70	0	24	0	0
T71	0	160	0	0
T72	0	241	0	0
T74	0	1	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	110366	0	0
T4	145461	207	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	1	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	71	0	0
T53	0	110	0	0
T64	0	153	0	0
T65	0	87	0	0
T70	0	24	0	0
T71	0	160	0	0
T72	0	241	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T98
1	1	Covered	T2,T5,T10

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T34,T35,T26

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T26
0	1	Covered	T34,T35,T26
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T34,T35,T26

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T34,T35,T26
1	0	Covered	T34,T35,T26

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T35,T26
1	1	Covered	T34,T35,T26

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T26
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T34,T35,T26

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T34,T35,T26

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T26
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T35,T26

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T26
1	0	Not Covered
1	1	Covered	T34,T35,T26

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T34,T35,T26
1	0	-	Covered	T34,T35,T26
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	393866125	393693293	0	0
NoSramReadWhenEmpty_A	393866125	370403466	0	0
NoSramWriteWhenFull_A	393866125	204810	0	0
OupBufWreadyAfterSramRead_A	393866125	115878	0	0
SramRvalidAfterRead_A	393866125	115878	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	370403466	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	204810	0	0
T26	0	192	0	0
T34	178725	2718	0	0
T35	156197	2564	0	0
T46	46846	0	0	0
T50	180557	0	0	0
T52	5802	0	0	0
T53	96095	0	0	0
T70	21619	0	0	0
T71	121905	0	0	0
T72	143070	0	0	0
T80	1639	0	0	0
T82	0	557	0	0
T83	0	4930	0	0
T98	0	3683	0	0
T109	0	808	0	0
T169	0	3618	0	0
T170	0	3906	0	0
T171	0	8	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	115878	0	0
T26	0	1178	0	0
T34	178725	868	0	0
T35	156197	744	0	0
T46	46846	0	0	0
T50	180557	0	0	0
T52	5802	0	0	0
T53	96095	0	0	0
T70	21619	0	0	0
T71	121905	0	0	0
T72	143070	0	0	0
T80	1639	0	0	0
T82	0	1116	0	0
T83	0	2976	0	0
T98	0	1054	0	0
T109	0	930	0	0
T169	0	1116	0	0
T170	0	1116	0	0
T172	0	868	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	115878	0	0
T26	0	1178	0	0
T34	178725	868	0	0
T35	156197	744	0	0
T46	46846	0	0	0
T50	180557	0	0	0
T52	5802	0	0	0
T53	96095	0	0	0
T70	21619	0	0	0
T71	121905	0	0	0
T72	143070	0	0	0
T80	1639	0	0	0
T82	0	1116	0	0
T83	0	2976	0	0
T98	0	1054	0	0
T109	0	930	0	0
T169	0	1116	0	0
T170	0	1116	0	0
T172	0	868	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T57,T58
1	1	Covered	T1,T4,T7

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T4,T7

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T4,T7

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T4,T7,T8

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T7
0	1	Covered	T4,T7,T8
1	0	Covered	T144,T145

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T144,T145
1	Covered	T1,T4,T7

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T144,T145
0	1	Covered	T1,T4,T7
1	0	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T4,T7,T8

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T7,T8

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T7,T8

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T59,T60
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T59,T60

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Not Covered
1	1	Covered	T1,T59,T60

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T7,T8
1	0	-	Covered	T1,T4,T7
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	393866125	393693293	0	0
NoSramReadWhenEmpty_A	393866125	165161994	0	0
NoSramWriteWhenFull_A	393866125	62635	0	0
OupBufWreadyAfterSramRead_A	393866125	236734	0	0
SramRvalidAfterRead_A	393866125	236734	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	165161994	0	0
T1	46021	544	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145375	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	1454	0	0
T8	96919	19656	0	0
T9	381897	16710	0	0
T10	9776	9312	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	62635	0	0
T1	46021	1000	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T57	0	8	0	0
T59	0	1371	0	0
T60	0	13	0	0
T69	0	853	0	0
T150	0	1758	0	0
T151	0	1624	0	0
T152	0	1426	0	0
T153	0	26	0	0
T154	0	8	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	236734	0	0
T4	145461	1	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	256	0	0
T8	96919	41	0	0
T9	381897	509	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	35	0	0
T52	0	2	0	0
T53	0	248	0	0
T64	0	314	0	0
T65	0	59	0	0
T70	0	55	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	236734	0	0
T4	145461	1	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	256	0	0
T8	96919	41	0	0
T9	381897	509	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	35	0	0
T52	0	2	0	0
T53	0	248	0	0
T64	0	314	0	0
T65	0	59	0	0
T70	0	55	0	0