Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf	91.67	100.00	66.67			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	100.00	72.73			90.91	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	88.21	100.00	80.00			84.62

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	412611951	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	412611951	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	412611951	0	0
T1	92042	46004	0	0
T2	194550	30579	0	0
T3	10146	0	0	0
T4	1163688	3885	0	0
T5	152592	11584	0	0
T6	137128	14514	0	0
T7	359464	44021	0	0
T8	775352	94608	0	0
T9	3055176	382108	0	0
T10	78208	4964	0	0
T18	0	56048	0	0
T34	0	173307	0	0
T35	0	140410	0	0
T37	47016	6895	0	0
T46	0	41416	0	0
T48	4738	536	0	0
T50	0	13	0	0
T51	53084	8740	0	0
T52	0	579	0	0
T64	0	57343	0	0
T65	0	59478	0	0
T74	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	368168	367640	0	0
T2	259400	258880	0	0
T3	13528	12896	0	0
T4	1163688	1163144	0	0
T5	152592	148184	0	0
T6	137128	136448	0	0
T7	359464	358880	0	0
T8	775352	774808	0	0
T9	3055176	3055136	0	0
T10	78208	74496	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	368168	367640	0	0
T2	259400	258880	0	0
T3	13528	12896	0	0
T4	1163688	1163144	0	0
T5	152592	148184	0	0
T6	137128	136448	0	0
T7	359464	358880	0	0
T8	775352	774808	0	0
T9	3055176	3055136	0	0
T10	78208	74496	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	368168	367640	0	0
T2	259400	258880	0	0
T3	13528	12896	0	0
T4	1163688	1163144	0	0
T5	152592	148184	0	0
T6	137128	136448	0	0
T7	359464	358880	0	0
T8	775352	774808	0	0
T9	3055176	3055136	0	0
T10	78208	74496	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	412611951	0	0
T1	92042	46004	0	0
T2	194550	30579	0	0
T3	10146	0	0	0
T4	1163688	3885	0	0
T5	152592	11584	0	0
T6	137128	14514	0	0
T7	359464	44021	0	0
T8	775352	94608	0	0
T9	3055176	382108	0	0
T10	78208	4964	0	0
T18	0	56048	0	0
T34	0	173307	0	0
T35	0	140410	0	0
T37	47016	6895	0	0
T46	0	41416	0	0
T48	4738	536	0	0
T50	0	13	0	0
T51	53084	8740	0	0
T52	0	579	0	0
T64	0	57343	0	0
T65	0	59478	0	0
T74	0	285	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	16	66.67
Logical	24	16	66.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	203126	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	203126	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	203126	0	0
T2	32425	63	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	9	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	14	0	0
T18	0	214	0	0
T26	0	1216	0	0
T34	0	896	0	0
T35	0	768	0	0
T37	7836	0	0	0
T46	0	78	0	0
T47	0	605	0	0
T50	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	203126	0	0
T2	32425	63	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	9	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	14	0	0
T18	0	214	0	0
T26	0	1216	0	0
T34	0	896	0	0
T35	0	768	0	0
T37	7836	0	0	0
T46	0	78	0	0
T47	0	605	0	0
T50	0	13	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T26,T28
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T26,T28
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	208248	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	208248	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	208248	0	0
T2	32425	53	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	113	0	0
T6	17141	89	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	66	0	0
T18	0	36	0	0
T34	0	28	0	0
T35	0	24	0	0
T37	7836	62	0	0
T46	0	148	0	0
T48	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	208248	0	0
T2	32425	53	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	113	0	0
T6	17141	89	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	66	0	0
T18	0	36	0	0
T34	0	28	0	0
T35	0	24	0	0
T37	7836	62	0	0
T46	0	148	0	0
T48	0	2	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T51

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T51

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T51,T173,T79
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T51

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T51

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T51

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T51,T173,T79
1	0	Covered	T4,T8,T51
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T51
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T51
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T51

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T51
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	160149	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	160149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	160149	0	0
T4	145461	231	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	35	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	87	0	0
T53	0	152	0	0
T64	0	198	0	0
T65	0	102	0	0
T70	0	32	0	0
T71	0	657	0	0
T72	0	337	0	0
T74	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	160149	0	0
T4	145461	231	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	35	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	87	0	0
T53	0	152	0	0
T64	0	198	0	0
T65	0	102	0	0
T70	0	32	0	0
T71	0	657	0	0
T72	0	337	0	0
T74	0	8	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T174,T175,T176
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T174,T175,T176
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	316981	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	316981	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	316981	0	0
T1	46021	268	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	572	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	258	0	0
T8	96919	49	0	0
T9	381897	511	0	0
T10	9776	0	0	0
T51	0	54	0	0
T52	0	5	0	0
T64	0	362	0	0
T65	0	73	0	0
T74	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	316981	0	0
T1	46021	268	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	572	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	258	0	0
T8	96919	49	0	0
T9	381897	511	0	0
T10	9776	0	0	0
T51	0	54	0	0
T52	0	5	0	0
T64	0	362	0	0
T65	0	73	0	0
T74	0	2	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	113005476	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	113005476	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	113005476	0	0
T2	32425	30463	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	11462	0	0
T6	17141	14425	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	4884	0	0
T18	0	55798	0	0
T34	0	172383	0	0
T35	0	139618	0	0
T37	7836	6833	0	0
T46	0	41190	0	0
T48	0	534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	113005476	0	0
T2	32425	30463	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	11462	0	0
T6	17141	14425	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	4884	0	0
T18	0	55798	0	0
T34	0	172383	0	0
T35	0	139618	0	0
T37	7836	6833	0	0
T46	0	41190	0	0
T48	0	534	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T10
1	0	Covered	T2,T5,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	25522790	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	25522790	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	25522790	0	0
T2	32425	419	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	55	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	93	0	0
T18	0	4627	0	0
T26	0	237971	0	0
T34	0	170395	0	0
T35	0	149046	0	0
T37	7836	0	0	0
T46	0	2506	0	0
T47	0	3984	0	0
T50	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	25522790	0	0
T2	32425	419	0	0
T3	1691	0	0	0
T4	145461	0	0	0
T5	19074	55	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	0	0	0
T9	381897	0	0	0
T10	9776	93	0	0
T18	0	4627	0	0
T26	0	237971	0	0
T34	0	170395	0	0
T35	0	149046	0	0
T37	7836	0	0	0
T46	0	2506	0	0
T47	0	3984	0	0
T50	0	240	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T51

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T51

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T8,T51
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T51

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T51

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T51

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T51
1	0	Covered	T4,T8,T51
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T51
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T51
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T51

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T51
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	32596362	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	32596362	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	32596362	0	0
T4	145461	89170	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	87463	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	15255	0	0
T53	0	24565	0	0
T64	0	34888	0	0
T65	0	18340	0	0
T70	0	6167	0	0
T71	0	115767	0	0
T72	0	62356	0	0
T74	0	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	32596362	0	0
T4	145461	89170	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	0	0	0
T8	96919	87463	0	0
T9	381897	0	0	0
T10	9776	0	0	0
T37	7836	0	0	0
T48	2369	0	0	0
T51	26542	15255	0	0
T53	0	24565	0	0
T64	0	34888	0	0
T65	0	18340	0	0
T70	0	6167	0	0
T71	0	115767	0	0
T72	0	62356	0	0
T74	0	391	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T51,T70,T177
1	0	1	Covered	T1,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393866125	240598819	0	0
DepthKnown_A	393866125	393693293	0	0
RvalidKnown_A	393866125	393693293	0	0
WreadyKnown_A	393866125	393693293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393866125	240598819	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	240598819	0	0
T1	46021	45736	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	3313	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	43763	0	0
T8	96919	94559	0	0
T9	381897	381597	0	0
T10	9776	0	0	0
T51	0	8686	0	0
T52	0	574	0	0
T64	0	56981	0	0
T65	0	59405	0	0
T74	0	283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	393693293	0	0
T1	46021	45955	0	0
T2	32425	32360	0	0
T3	1691	1612	0	0
T4	145461	145393	0	0
T5	19074	18523	0	0
T6	17141	17056	0	0
T7	44933	44860	0	0
T8	96919	96851	0	0
T9	381897	381892	0	0
T10	9776	9312	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393866125	240598819	0	0
T1	46021	45736	0	0
T2	32425	0	0	0
T3	1691	0	0	0
T4	145461	3313	0	0
T5	19074	0	0	0
T6	17141	0	0	0
T7	44933	43763	0	0
T8	96919	94559	0	0
T9	381897	381597	0	0
T10	9776	0	0	0
T51	0	8686	0	0
T52	0	574	0	0
T64	0	56981	0	0
T65	0	59405	0	0
T74	0	283	0	0