Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.19	85.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	85.19	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	8	19	70.37

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	8	19	70.37	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

162835

1

T1

548

T2

159

T3

1

ack

282

1

T17

9

T18

3

T19

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	660	1			T2	2		T27	5		T152	1
high	34420	1			T1	115		T2	48		T5	1
med	61961	1			T1	235		T2	53		T5	2
sml	65379	1			T1	196		T2	56		T3	1
all_zero	697	1			T1	2		T13	1		T27	4

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81204

1

T1

276

T2

87

T5

2

auto[1]

81913

1

T1

272

T2

72

T3

1

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111227

1

T1

362

T2

108

T3

1

auto[1]

51890

1

T1

186

T2

51

T8

11

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159360

1

T1

547

T2

159

T3

1

auto[1]

3757

1

T1

1

T8

25

T13

2

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156354

1

T1

544

T2

145

T5

1

auto[1]

6763

1

T1

4

T2

14

T3

1

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157190

1

T1

545

T2

145

T3

1

auto[1]

5927

1

T1

3

T2

14

T5

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81204

1

T1

276

T2

87

T5

2

auto[1]

81913

1

T1

272

T2

72

T3

1

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111227

1

T1

362

T2

108

T3

1

auto[1]

51890

1

T1

186

T2

51

T8

11

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159360

1

T1

547

T2

159

T3

1

auto[1]

3757

1

T1

1

T8

25

T13

2

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156354

1

T1

544

T2

145

T5

1

auto[1]

6763

1

T1

4

T2

14

T3

1

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157190

1

T1

545

T2

145

T3

1

auto[1]

5927

1

T1

3

T2

14

T5

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	8	19	70.37	6
Automatically Generated Cross Bins	15	6	9	60.00	6
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

9

1

T234

1

T235

1

T236

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T237

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T238

1

T239

1

T240

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T241

1

T242

1

T243

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T236

1

T244

1

T245

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T124

1

T243

1

T236

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

9

1

T18

1

T246

1

T243

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T124

1

T247

1

-

-

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T19

1

T234

1

T241

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	49263	1			T1	178		T2	50		T13	3
write_address_byte	6763	1			T1	4		T2	14		T3	1
read_with_ack	841	1			T8	11		T13	1		T17	2
read_with_nack	2916	1			T1	1		T8	14		T13	1
stop_byte	5927	1			T1	3		T2	14		T5	1
write_address_byte_nak	6663	1			T1	4		T2	14		T3	1
data_byte_nack	162835	1			T1	548		T2	159		T3	1
stop_byte_nack	5872	1			T1	3		T2	14		T5	1
nakok_byte_nack	81766	1			T1	272		T2	72		T3	1
nakok_addr_byte_nack	3335	1			T1	1		T2	6		T3	1