Group : i2c_env_pkg::i2c_scl_sda_override_cg
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Group : i2c_env_pkg::i2c_scl_sda_override_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.scl_sda_override_cg 100.00 1 100 1 64 64



Group Instance : i2c_env_pkg.scl_sda_override_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance i2c_env_pkg.scl_sda_override_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_sclval 2 0 2 100.00 100 1 1 2
cp_sdaval 2 0 2 100.00 100 1 1 2
cp_txorvden 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_txorvden_x_sclval 4 0 4 100.00 100 1 1 0
cp_txorvden_x_sdaval 4 0 4 100.00 100 1 1 0


Summary for Variable cp_sclval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sclval

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 394 1 T71 10 T88 8 T89 8
auto[1] 371 1 T71 6 T88 8 T89 4


Summary for Variable cp_sdaval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sdaval

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 374 1 T71 7 T88 9 T89 7
auto[1] 391 1 T71 9 T88 7 T89 5


Summary for Variable cp_txorvden

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txorvden

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 369 1 T71 9 T88 8 T89 3
auto[1] 396 1 T71 7 T88 8 T89 9


Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins
cp_txorvdencp_sclvalCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 168 1 T71 6 T88 3 T89 2
auto[0] auto[1] 201 1 T71 3 T88 5 T89 1
auto[1] auto[0] 226 1 T71 4 T88 5 T89 6
auto[1] auto[1] 170 1 T71 3 T88 3 T89 3


Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins
cp_txorvdencp_sdavalCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 190 1 T71 3 T88 5 T89 2
auto[0] auto[1] 179 1 T71 6 T88 3 T89 1
auto[1] auto[0] 184 1 T71 4 T88 4 T89 5
auto[1] auto[1] 212 1 T71 3 T88 4 T89 4

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