Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28747039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7984291

1

T1

24018

T2

7872

T3

82399

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35930288	1			T1	164228		T2	15726		T3	314603
values[0x0]	399565	1			T1	1938		T2	140		T3	3165
values[0x1]	401477	1			T1	2040		T2	127		T3	3125

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20115766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16615564

1

T1

68589

T2

9531

T3

150843

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	149392	1			T1	29		T3	1305		T6	6
valid_sources[0x01]	132534	1			T1	304		T3	1297		T6	9
valid_sources[0x02]	134271	1			T1	311		T3	1266		T6	6
valid_sources[0x03]	137567	1			T1	2400		T3	1336		T6	1
valid_sources[0x04]	141974	1			T1	1329		T3	1251		T6	8
valid_sources[0x05]	138038	1			T1	21		T3	1299		T6	7
valid_sources[0x06]	145665	1			T1	782		T3	1216		T6	8
valid_sources[0x07]	160378	1			T1	2232		T3	1276		T6	7
valid_sources[0x08]	132629	1			T1	1217		T3	1235		T6	9
valid_sources[0x09]	138298	1			T1	1210		T3	1297		T6	5
valid_sources[0x0a]	137125	1			T1	647		T3	1250		T6	11
valid_sources[0x0b]	152774	1			T1	1243		T3	1280		T6	5
valid_sources[0x0c]	132893	1			T1	17		T3	1219		T6	3
valid_sources[0x0d]	132054	1			T1	753		T3	1265		T6	5
valid_sources[0x0e]	141148	1			T1	5010		T3	1196		T7	16
valid_sources[0x0f]	129457	1			T1	898		T3	1313		T6	5
valid_sources[0x10]	141758	1			T1	16		T3	1286		T6	6
valid_sources[0x11]	128620	1			T1	617		T3	1321		T6	5
valid_sources[0x12]	145840	1			T1	44		T3	1200		T6	8
valid_sources[0x13]	154836	1			T1	1195		T3	1135		T6	9
valid_sources[0x14]	148884	1			T1	26		T3	1293		T6	4
valid_sources[0x15]	136892	1			T1	36		T3	1296		T6	7
valid_sources[0x16]	153419	1			T1	1376		T3	1236		T5	1
valid_sources[0x17]	152773	1			T1	21		T3	1349		T5	2
valid_sources[0x18]	148629	1			T1	3572		T3	1284		T6	6
valid_sources[0x19]	145550	1			T1	912		T3	1347		T6	5
valid_sources[0x1a]	135881	1			T1	2404		T3	1258		T5	1
valid_sources[0x1b]	151500	1			T1	2987		T3	1259		T6	6
valid_sources[0x1c]	145892	1			T1	37		T3	1233		T6	4
valid_sources[0x1d]	153036	1			T1	903		T3	1207		T6	1
valid_sources[0x1e]	142372	1			T1	36		T3	1212		T6	4
valid_sources[0x1f]	138776	1			T1	595		T3	1278		T5	634
valid_sources[0x20]	143043	1			T1	2238		T3	1224		T5	1
valid_sources[0x21]	137164	1			T1	609		T3	1262		T6	2
valid_sources[0x22]	139902	1			T1	22		T3	1306		T6	10
valid_sources[0x23]	141530	1			T1	7		T3	1247		T6	3
valid_sources[0x24]	141337	1			T1	156		T3	1252		T6	2
valid_sources[0x25]	144041	1			T1	24		T3	1276		T6	2
valid_sources[0x26]	143312	1			T1	15		T3	1200		T5	8
valid_sources[0x27]	136245	1			T1	310		T3	1251		T6	3
valid_sources[0x28]	151301	1			T1	19		T3	1245		T5	1
valid_sources[0x29]	157381	1			T1	2206		T3	1227		T6	5
valid_sources[0x2a]	126354	1			T1	9		T3	1339		T6	9
valid_sources[0x2b]	137247	1			T1	2924		T3	1306		T6	7
valid_sources[0x2c]	148013	1			T1	1336		T3	1176		T5	1
valid_sources[0x2d]	138992	1			T1	29		T3	1255		T5	1
valid_sources[0x2e]	151295	1			T1	604		T3	1257		T6	3
valid_sources[0x2f]	138993	1			T1	3		T3	1257		T6	8
valid_sources[0x30]	140670	1			T1	16		T3	1326		T6	4
valid_sources[0x31]	148198	1			T1	903		T3	1306		T6	9
valid_sources[0x32]	128493	1			T1	19		T3	1266		T6	1
valid_sources[0x33]	167151	1			T1	163		T3	1194		T6	9
valid_sources[0x34]	136133	1			T1	3		T3	1241		T6	4
valid_sources[0x35]	161208	1			T1	4449		T2	15993		T3	1262
valid_sources[0x36]	139543	1			T1	1168		T3	1246		T6	7
valid_sources[0x37]	140726	1			T1	165		T3	1167		T6	6
valid_sources[0x38]	137313	1			T1	32		T3	1256		T6	8
valid_sources[0x39]	172506	1			T1	476		T3	1200		T6	4
valid_sources[0x3a]	141924	1			T1	303		T3	1232		T6	7
valid_sources[0x3b]	140862	1			T1	1059		T3	1231		T6	4
valid_sources[0x3c]	144447	1			T1	1660		T3	1254		T4	1050
valid_sources[0x3d]	135096	1			T1	1559		T3	1294		T5	1
valid_sources[0x3e]	157044	1			T1	20		T3	1172		T6	9
valid_sources[0x3f]	166126	1			T1	1209		T3	1298		T6	7
valid_sources[0x40]	142927	1			T1	1062		T3	1196		T6	6
valid_sources[0x41]	134313	1			T1	892		T3	1192		T6	6
valid_sources[0x42]	148481	1			T1	2674		T3	1261		T6	5
valid_sources[0x43]	144473	1			T1	3091		T3	1339		T6	9
valid_sources[0x44]	136235	1			T1	902		T3	1254		T6	6
valid_sources[0x45]	143364	1			T1	25		T3	1252		T5	1
valid_sources[0x46]	133350	1			T1	10		T3	1200		T6	8
valid_sources[0x47]	134352	1			T1	19		T3	1220		T6	9
valid_sources[0x48]	140639	1			T1	15		T3	1232		T6	3
valid_sources[0x49]	145541	1			T1	1824		T3	1219		T6	4
valid_sources[0x4a]	128659	1			T1	1084		T3	1192		T5	1
valid_sources[0x4b]	153434	1			T1	939		T3	1255		T6	2
valid_sources[0x4c]	145372	1			T1	18		T3	1232		T6	5
valid_sources[0x4d]	155560	1			T1	1473		T3	1345		T6	8
valid_sources[0x4e]	140647	1			T1	32		T3	1255		T6	6
valid_sources[0x4f]	140303	1			T1	25		T3	1205		T6	6
valid_sources[0x50]	141954	1			T1	8		T3	1213		T6	3
valid_sources[0x51]	136731	1			T1	13		T3	1241		T6	5
valid_sources[0x52]	135072	1			T1	919		T3	1244		T6	3
valid_sources[0x53]	140209	1			T1	21		T3	1276		T5	1
valid_sources[0x54]	135518	1			T1	1044		T3	1310		T5	2
valid_sources[0x55]	144432	1			T1	180		T3	1227		T5	1
valid_sources[0x56]	131759	1			T1	464		T3	1244		T6	8
valid_sources[0x57]	146736	1			T1	17		T3	1248		T6	6
valid_sources[0x58]	147055	1			T1	157		T3	1226		T5	1
valid_sources[0x59]	141544	1			T1	18		T3	1220		T6	10
valid_sources[0x5a]	137832	1			T1	24		T3	1289		T6	4
valid_sources[0x5b]	129617	1			T1	25		T3	1250		T6	6
valid_sources[0x5c]	144292	1			T1	456		T3	1313		T6	4
valid_sources[0x5d]	139097	1			T1	13		T3	1269		T6	8
valid_sources[0x5e]	147788	1			T1	29		T3	1248		T6	7
valid_sources[0x5f]	147286	1			T1	17		T3	1201		T6	9
valid_sources[0x60]	169353	1			T1	169		T3	1201		T5	1
valid_sources[0x61]	130618	1			T1	35		T3	1241		T6	2
valid_sources[0x62]	161763	1			T1	740		T3	1330		T6	8
valid_sources[0x63]	131553	1			T1	18		T3	1286		T7	42
valid_sources[0x64]	140154	1			T1	9		T3	1275		T6	5
valid_sources[0x65]	140748	1			T1	1076		T3	1228		T6	7
valid_sources[0x66]	153468	1			T1	2213		T3	1264		T6	6
valid_sources[0x67]	132667	1			T1	1344		T3	1264		T6	3
valid_sources[0x68]	148365	1			T1	631		T3	1306		T6	3
valid_sources[0x69]	148487	1			T1	1042		T3	1224		T5	1
valid_sources[0x6a]	155886	1			T1	9		T3	1215		T6	5
valid_sources[0x6b]	150044	1			T1	343		T3	1296		T6	8
valid_sources[0x6c]	141401	1			T1	3290		T3	1211		T6	7
valid_sources[0x6d]	143103	1			T1	15		T3	1289		T5	1
valid_sources[0x6e]	141422	1			T1	895		T3	1197		T6	5
valid_sources[0x6f]	132085	1			T1	16		T3	1232		T6	7
valid_sources[0x70]	145411	1			T1	183		T3	1271		T6	5
valid_sources[0x71]	134754	1			T1	159		T3	1274		T6	5
valid_sources[0x72]	131349	1			T1	43		T3	1258		T6	8
valid_sources[0x73]	150406	1			T1	2074		T3	1220		T6	5
valid_sources[0x74]	147445	1			T1	22		T3	1298		T6	16
valid_sources[0x75]	136911	1			T1	740		T3	1228		T6	9
valid_sources[0x76]	147206	1			T1	349		T3	1271		T6	3
valid_sources[0x77]	147283	1			T1	1367		T3	1258		T6	10
valid_sources[0x78]	132446	1			T1	13		T3	1263		T6	12
valid_sources[0x79]	141723	1			T1	13		T3	1232		T5	8
valid_sources[0x7a]	128243	1			T1	760		T3	1265		T6	6
valid_sources[0x7b]	132672	1			T1	12		T3	1189		T6	6
valid_sources[0x7c]	171999	1			T1	744		T3	1201		T6	1
valid_sources[0x7d]	138288	1			T1	3281		T3	1281		T6	6
valid_sources[0x7e]	132051	1			T1	42		T3	1244		T5	1
valid_sources[0x7f]	144540	1			T1	44		T3	1248		T6	11
valid_sources[0x80]	149487	1			T1	7		T3	1283		T6	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7629616

1

T1

22667

T2

7707

T3

80298

values[0x0]

all_enables

biggest_size

210338

1

T1

890

T2

93

T3

1398

values[0x1]

all_enables

biggest_size

144337

1

T1

461

T2

72

T3

703