Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	404072205	0	0	0
ctrl_rd_A	404072205	1961	0	0
host_fifo_config_rd_A	404072205	4138	0	0
host_nack_handler_timeout_rd_A	404072205	1412	0	0
host_timeout_ctrl_rd_A	404072205	1151	0	0
intr_enable_rd_A	404072205	3451	0	0
ovrd_rd_A	404072205	2435	0	0
target_fifo_config_rd_A	404072205	1211	0	0
target_id_rd_A	404072205	1667	0	0
target_timeout_ctrl_rd_A	404072205	1314	0	0
timeout_ctrl_rd_A	404072205	1460	0	0
timing0_rd_A	404072205	1477	0	0
timing1_rd_A	404072205	1396	0	0
timing2_rd_A	404072205	1274	0	0
timing3_rd_A	404072205	1313	0	0
timing4_rd_A	404072205	1413	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1961	0	0
T92	2574	15	0	0
T93	2683	6	0	0
T94	2220	27	0	0
T95	2113	5	0	0
T96	8159	19	0	0
T97	3649	39	0	0
T98	14164	333	0	0
T99	2161	35	0	0
T100	2977	11	0	0
T101	9952	38	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	4138	0	0
T34	369916	0	0	0
T69	130582	0	0	0
T74	492177	195	0	0
T83	83391	0	0	0
T84	21915	0	0	0
T85	341060	0	0	0
T86	202401	0	0	0
T87	1143	0	0	0
T102	0	170	0	0
T103	0	148	0	0
T104	0	139	0	0
T105	0	375	0	0
T106	0	102	0	0
T107	0	114	0	0
T108	0	180	0	0
T109	0	91	0	0
T110	0	171	0	0
T111	23384	0	0	0
T112	19816	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1412	0	0
T92	2574	19	0	0
T93	2683	4	0	0
T94	2220	9	0	0
T95	2113	6	0	0
T96	8159	23	0	0
T97	3649	23	0	0
T98	14164	111	0	0
T99	2161	3	0	0
T100	2977	12	0	0
T101	9952	26	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1151	0	0
T92	2574	1	0	0
T93	2683	1	0	0
T95	2113	8	0	0
T96	8159	22	0	0
T97	3649	17	0	0
T98	14164	74	0	0
T99	2161	3	0	0
T100	2977	20	0	0
T101	9952	17	0	0
T113	3226	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	3451	0	0
T93	0	88	0	0
T94	0	6	0	0
T95	0	51	0	0
T96	0	24	0	0
T97	0	106	0	0
T98	0	611	0	0
T100	0	48	0	0
T105	864216	45	0	0
T114	0	7	0	0
T115	0	4	0	0
T116	21982	0	0	0
T117	9902	0	0	0
T118	105735	0	0	0
T119	13161	0	0	0
T120	67885	0	0	0
T121	15954	0	0	0
T122	4792	0	0	0
T123	5980	0	0	0
T124	55368	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	2435	0	0
T72	0	52	0	0
T76	137535	0	0	0
T125	1375	66	0	0
T126	0	37	0	0
T127	0	36	0	0
T128	0	71	0	0
T129	0	71	0	0
T130	0	46	0	0
T131	0	46	0	0
T132	0	83	0	0
T133	0	31	0	0
T134	77452	0	0	0
T135	29090	0	0	0
T136	360018	0	0	0
T137	35841	0	0	0
T138	6521	0	0	0
T139	123571	0	0	0
T140	1053	0	0	0
T141	40509	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1211	0	0
T92	2574	18	0	0
T93	2683	7	0	0
T94	2220	9	0	0
T95	2113	5	0	0
T96	8159	8	0	0
T97	3649	13	0	0
T98	14164	132	0	0
T99	2161	9	0	0
T100	2977	6	0	0
T101	9952	26	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1667	0	0
T92	2574	18	0	0
T93	2683	18	0	0
T94	2220	4	0	0
T95	2113	7	0	0
T96	8159	22	0	0
T97	3649	32	0	0
T98	14164	255	0	0
T99	2161	3	0	0
T100	2977	25	0	0
T101	9952	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1314	0	0
T92	2574	3	0	0
T93	2683	8	0	0
T94	2220	10	0	0
T95	2113	9	0	0
T96	8159	2	0	0
T97	3649	16	0	0
T98	14164	118	0	0
T99	2161	1	0	0
T100	2977	23	0	0
T101	9952	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1460	0	0
T92	2574	6	0	0
T93	2683	5	0	0
T94	2220	14	0	0
T95	2113	4	0	0
T96	8159	25	0	0
T97	3649	24	0	0
T98	14164	117	0	0
T100	2977	13	0	0
T101	9952	22	0	0
T113	3226	2	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1477	0	0
T92	2574	12	0	0
T93	2683	11	0	0
T94	2220	17	0	0
T95	2113	4	0	0
T96	8159	14	0	0
T97	3649	29	0	0
T98	14164	136	0	0
T99	2161	12	0	0
T100	2977	22	0	0
T101	9952	19	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1396	0	0
T92	2574	10	0	0
T93	2683	18	0	0
T94	2220	11	0	0
T95	2113	7	0	0
T96	8159	9	0	0
T97	3649	29	0	0
T98	14164	132	0	0
T99	2161	4	0	0
T100	2977	18	0	0
T101	9952	22	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1274	0	0
T92	2574	9	0	0
T94	2220	19	0	0
T95	2113	9	0	0
T96	8159	20	0	0
T97	3649	18	0	0
T98	14164	135	0	0
T100	2977	20	0	0
T101	9952	30	0	0
T113	3226	1	0	0
T142	12798	26	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1313	0	0
T92	2574	5	0	0
T93	2683	19	0	0
T94	2220	12	0	0
T95	2113	8	0	0
T96	8159	17	0	0
T97	3649	9	0	0
T98	14164	66	0	0
T99	2161	1	0	0
T100	2977	18	0	0
T101	9952	19	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404072205	1413	0	0
T92	2574	2	0	0
T93	2683	11	0	0
T94	2220	10	0	0
T95	2113	10	0	0
T96	8159	34	0	0
T97	3649	18	0	0
T98	14164	119	0	0
T100	2977	29	0	0
T101	9952	29	0	0
T113	3226	17	0	0