Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27926904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7607046

1

T1

48

T2

9934

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34661965	1			T1	115		T2	20580		T3	55
values[0x0]	431509	1			T1	62		T2	57		T3	39
values[0x1]	440476	1			T1	47		T2	74		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19527897	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16006053

1

T1

98

T2

12175

T3

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	135240	1			T2	208		T4	2		T7	506
valid_sources[0x01]	130305	1			T2	48		T4	5		T6	1
valid_sources[0x02]	206782	1			T1	11		T2	143		T4	7
valid_sources[0x03]	124323	1			T1	4		T2	113		T4	9
valid_sources[0x04]	134757	1			T2	89		T4	1		T6	2
valid_sources[0x05]	127130	1			T1	3		T2	22		T4	4
valid_sources[0x06]	128802	1			T1	2		T2	128		T4	6
valid_sources[0x07]	137650	1			T1	6		T2	135		T4	1
valid_sources[0x08]	131260	1			T2	49		T4	4		T7	502
valid_sources[0x09]	133586	1			T2	56		T4	8		T7	3
valid_sources[0x0a]	129885	1			T2	83		T4	1		T6	3
valid_sources[0x0b]	134541	1			T2	162		T4	4		T7	16
valid_sources[0x0c]	122688	1			T2	143		T4	7		T6	1
valid_sources[0x0d]	129564	1			T2	133		T4	2		T6	1
valid_sources[0x0e]	148873	1			T2	42		T4	3		T7	514
valid_sources[0x0f]	132892	1			T2	136		T3	6		T4	1
valid_sources[0x10]	141576	1			T2	63		T3	9		T4	2
valid_sources[0x11]	133917	1			T1	5		T2	16		T4	3
valid_sources[0x12]	143686	1			T2	62		T4	5		T7	511
valid_sources[0x13]	135152	1			T2	116		T4	1		T7	504
valid_sources[0x14]	129686	1			T2	18		T4	3		T6	1
valid_sources[0x15]	146401	1			T2	82		T4	6		T7	4
valid_sources[0x16]	138034	1			T2	38		T4	4		T7	10
valid_sources[0x17]	154072	1			T2	45		T4	4		T7	509
valid_sources[0x18]	137367	1			T2	52		T4	3		T6	1
valid_sources[0x19]	152916	1			T1	7		T2	32		T3	7
valid_sources[0x1a]	131584	1			T1	9		T2	39		T4	4
valid_sources[0x1b]	136094	1			T2	93		T4	5		T7	503
valid_sources[0x1c]	138607	1			T2	78		T4	6		T6	1
valid_sources[0x1d]	128709	1			T1	1		T2	37		T4	4
valid_sources[0x1e]	135267	1			T2	188		T4	1		T7	5
valid_sources[0x1f]	141679	1			T2	128		T4	8		T6	1
valid_sources[0x20]	138135	1			T2	128		T4	4		T7	6
valid_sources[0x21]	135432	1			T2	151		T4	4		T7	507
valid_sources[0x22]	137717	1			T2	31		T4	6		T6	1
valid_sources[0x23]	134457	1			T2	68		T4	10		T7	1010
valid_sources[0x24]	132024	1			T2	95		T4	3		T6	2
valid_sources[0x25]	173322	1			T1	7		T2	87		T4	7
valid_sources[0x26]	126870	1			T2	24		T4	7		T6	1
valid_sources[0x27]	127359	1			T2	181		T3	12		T4	4
valid_sources[0x28]	126581	1			T2	72		T4	8		T7	949
valid_sources[0x29]	122905	1			T2	117		T4	6		T6	2
valid_sources[0x2a]	138722	1			T2	18		T4	5		T6	3
valid_sources[0x2b]	148540	1			T1	7		T2	198		T4	11
valid_sources[0x2c]	127201	1			T2	43		T4	2		T6	1
valid_sources[0x2d]	163604	1			T1	3		T2	21		T4	1
valid_sources[0x2e]	125553	1			T2	20		T4	8		T7	5
valid_sources[0x2f]	145832	1			T2	32		T4	13		T7	507
valid_sources[0x30]	141511	1			T2	112		T4	6		T6	1
valid_sources[0x31]	131576	1			T2	98		T4	4		T6	2
valid_sources[0x32]	156421	1			T2	78		T4	6		T6	3
valid_sources[0x33]	141336	1			T2	17		T4	5		T6	2
valid_sources[0x34]	137431	1			T2	110		T4	6		T7	512
valid_sources[0x35]	145909	1			T2	52		T4	5		T6	2
valid_sources[0x36]	140874	1			T2	25		T4	11		T6	4
valid_sources[0x37]	131661	1			T2	160		T4	5		T7	13
valid_sources[0x38]	128862	1			T2	92		T4	3		T6	1
valid_sources[0x39]	124284	1			T2	54		T4	7		T6	3
valid_sources[0x3a]	143869	1			T2	60		T4	7		T6	1
valid_sources[0x3b]	141868	1			T2	195		T7	1016		T10	33
valid_sources[0x3c]	134164	1			T2	26		T4	4		T7	512
valid_sources[0x3d]	155080	1			T2	100		T4	3		T6	1
valid_sources[0x3e]	136402	1			T2	5		T4	1		T6	1
valid_sources[0x3f]	133220	1			T2	141		T4	9		T6	3
valid_sources[0x40]	160226	1			T1	2		T2	97		T4	3
valid_sources[0x41]	151402	1			T2	108		T4	7		T6	1
valid_sources[0x42]	146633	1			T2	49		T4	13		T7	9
valid_sources[0x43]	136323	1			T2	26		T4	9		T6	1
valid_sources[0x44]	140798	1			T2	125		T4	6		T7	7
valid_sources[0x45]	143351	1			T2	190		T3	2		T4	11
valid_sources[0x46]	151252	1			T1	2		T2	26		T4	13
valid_sources[0x47]	135950	1			T2	73		T4	4		T6	2
valid_sources[0x48]	123142	1			T1	1		T2	129		T4	9
valid_sources[0x49]	128237	1			T2	24		T4	2		T6	1
valid_sources[0x4a]	129775	1			T2	115		T4	5		T6	3
valid_sources[0x4b]	136689	1			T2	126		T4	6		T7	501
valid_sources[0x4c]	136334	1			T2	7		T4	9		T6	4
valid_sources[0x4d]	135862	1			T1	1		T2	138		T4	9
valid_sources[0x4e]	139893	1			T2	48		T4	9		T6	1
valid_sources[0x4f]	116103	1			T2	25		T4	11		T6	2
valid_sources[0x50]	179287	1			T1	10		T2	19		T4	8
valid_sources[0x51]	142356	1			T2	39		T4	11		T7	9
valid_sources[0x52]	153110	1			T1	1		T2	65		T4	5
valid_sources[0x53]	134004	1			T2	82		T4	10		T7	509
valid_sources[0x54]	151858	1			T2	2		T4	3		T6	1
valid_sources[0x55]	154024	1			T2	87		T4	11		T6	1
valid_sources[0x56]	135909	1			T2	67		T4	8		T7	11
valid_sources[0x57]	134111	1			T2	46		T4	9		T7	516
valid_sources[0x58]	142059	1			T2	33		T4	4		T6	1
valid_sources[0x59]	136010	1			T2	36		T4	4		T7	8
valid_sources[0x5a]	136346	1			T2	138		T4	5		T6	1
valid_sources[0x5b]	135319	1			T2	83		T4	2		T7	10
valid_sources[0x5c]	144737	1			T2	129		T4	7		T6	1
valid_sources[0x5d]	143346	1			T2	116		T4	11		T7	5
valid_sources[0x5e]	133028	1			T2	123		T4	4		T7	1017
valid_sources[0x5f]	123530	1			T2	43		T4	2		T6	1
valid_sources[0x60]	129817	1			T2	76		T4	5		T6	1
valid_sources[0x61]	124287	1			T2	68		T4	2		T6	1
valid_sources[0x62]	151197	1			T2	51		T5	106		T7	2009
valid_sources[0x63]	148347	1			T2	25		T4	6		T7	12
valid_sources[0x64]	126365	1			T2	152		T4	2		T6	4
valid_sources[0x65]	154681	1			T1	5		T2	20		T4	2
valid_sources[0x66]	161918	1			T2	40		T4	6		T6	2
valid_sources[0x67]	133840	1			T1	3		T2	196		T4	8
valid_sources[0x68]	144128	1			T1	2		T2	168		T3	1
valid_sources[0x69]	136220	1			T2	31		T4	4		T6	1
valid_sources[0x6a]	173063	1			T2	54		T4	2		T7	2
valid_sources[0x6b]	127322	1			T2	137		T4	3		T6	1
valid_sources[0x6c]	137713	1			T1	3		T2	58		T4	10
valid_sources[0x6d]	132451	1			T2	136		T4	9		T6	1
valid_sources[0x6e]	143975	1			T2	45		T4	7		T6	1
valid_sources[0x6f]	131907	1			T1	2		T2	26		T4	3
valid_sources[0x70]	128865	1			T1	18		T2	58		T4	3
valid_sources[0x71]	145125	1			T2	8		T4	3		T6	3
valid_sources[0x72]	145499	1			T2	61		T3	5		T4	7
valid_sources[0x73]	170193	1			T2	41		T3	1		T4	12
valid_sources[0x74]	137848	1			T2	41		T4	5		T6	1
valid_sources[0x75]	134250	1			T2	114		T3	14		T4	8
valid_sources[0x76]	131482	1			T2	84		T4	6		T6	4
valid_sources[0x77]	140242	1			T2	78		T4	4		T7	518
valid_sources[0x78]	136615	1			T2	20		T4	1		T6	1
valid_sources[0x79]	139546	1			T2	93		T4	5		T6	3
valid_sources[0x7a]	139537	1			T2	26		T4	8		T6	2
valid_sources[0x7b]	153020	1			T1	1		T2	87		T4	12
valid_sources[0x7c]	129943	1			T2	65		T4	7		T6	1
valid_sources[0x7d]	128691	1			T1	1		T2	105		T4	8
valid_sources[0x7e]	153120	1			T2	27		T4	11		T7	8
valid_sources[0x7f]	143724	1			T1	11		T2	73		T4	9
valid_sources[0x80]	138880	1			T2	28		T4	2		T7	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7188992

1

T1

1

T2

9823

T3

5

values[0x0]

all_enables

biggest_size

242249

1

T1

34

T2

50

T3

18

values[0x1]

all_enables

biggest_size

175805

1

T1

13

T2

61

T3

8