Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26968698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6821796

1

T1

3

T2

15

T3

2317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33006550	1			T1	1		T2	17		T3	33030
values[0x0]	391519	1			T1	2		T2	14		T3	227
values[0x1]	392425	1			T1	5		T2	13		T3	252

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18772203	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15018291

1

T1

3

T2

22

T3

12316

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	126485	1			T4	22		T5	46		T6	93
valid_sources[0x01]	132649	1			T4	12		T5	27		T6	92
valid_sources[0x02]	124096	1			T3	1		T4	7		T5	30
valid_sources[0x03]	127325	1			T1	5		T3	2		T4	27
valid_sources[0x04]	130084	1			T3	505		T4	14		T5	33
valid_sources[0x05]	137806	1			T3	1		T4	39		T5	34
valid_sources[0x06]	125793	1			T4	24		T5	39		T6	93
valid_sources[0x07]	126340	1			T3	1004		T4	20		T5	32
valid_sources[0x08]	137995	1			T3	2		T4	33		T5	34
valid_sources[0x09]	122047	1			T3	1		T4	22		T5	41
valid_sources[0x0a]	129185	1			T3	2		T4	14		T5	39
valid_sources[0x0b]	145188	1			T4	37		T5	50		T6	111
valid_sources[0x0c]	125003	1			T3	1		T4	24		T5	24
valid_sources[0x0d]	126536	1			T4	7		T5	35		T6	69
valid_sources[0x0e]	128700	1			T3	2		T4	10		T5	34
valid_sources[0x0f]	128576	1			T4	32		T5	26		T6	105
valid_sources[0x10]	157871	1			T3	1		T4	31		T5	55
valid_sources[0x11]	134886	1			T3	1		T4	16		T5	35
valid_sources[0x12]	132958	1			T3	2		T4	20		T5	32
valid_sources[0x13]	131684	1			T3	1		T4	12		T5	56
valid_sources[0x14]	128147	1			T3	16		T4	14		T5	43
valid_sources[0x15]	120181	1			T3	2		T4	11		T5	34
valid_sources[0x16]	135191	1			T3	504		T4	25		T5	48
valid_sources[0x17]	126296	1			T4	14		T5	33		T6	87
valid_sources[0x18]	133909	1			T3	3		T4	9		T5	21
valid_sources[0x19]	141759	1			T4	5		T5	37		T6	77
valid_sources[0x1a]	128251	1			T3	2		T4	22		T5	35
valid_sources[0x1b]	134071	1			T4	27		T5	36		T6	113
valid_sources[0x1c]	143538	1			T3	1		T4	19		T5	33
valid_sources[0x1d]	128127	1			T3	511		T4	15		T5	33
valid_sources[0x1e]	119266	1			T3	517		T4	15		T5	23
valid_sources[0x1f]	135317	1			T3	510		T4	19		T5	47
valid_sources[0x20]	120849	1			T3	1		T4	28		T5	19
valid_sources[0x21]	133315	1			T3	2		T4	25		T5	31
valid_sources[0x22]	119216	1			T3	1		T4	9		T5	28
valid_sources[0x23]	129887	1			T3	3		T4	18		T5	51
valid_sources[0x24]	134293	1			T3	2		T4	21		T5	38
valid_sources[0x25]	126102	1			T4	52		T5	22		T6	91
valid_sources[0x26]	133939	1			T4	32		T5	44		T6	108
valid_sources[0x27]	136799	1			T3	1		T4	19		T5	31
valid_sources[0x28]	125375	1			T4	37		T5	38		T6	113
valid_sources[0x29]	154019	1			T3	2		T4	20		T5	26
valid_sources[0x2a]	152937	1			T3	1		T4	25		T5	24
valid_sources[0x2b]	145342	1			T3	1		T4	20		T5	37
valid_sources[0x2c]	164540	1			T3	1		T4	13		T5	27
valid_sources[0x2d]	143113	1			T3	1		T4	22		T5	21
valid_sources[0x2e]	128564	1			T3	1		T4	18		T5	36
valid_sources[0x2f]	128614	1			T3	508		T4	23		T5	33
valid_sources[0x30]	135425	1			T3	504		T4	14		T5	19
valid_sources[0x31]	131367	1			T3	2		T4	24		T5	36
valid_sources[0x32]	129440	1			T3	1		T4	14		T5	33
valid_sources[0x33]	118248	1			T3	513		T4	12		T5	27
valid_sources[0x34]	129609	1			T3	1		T4	15		T5	46
valid_sources[0x35]	125770	1			T3	2		T4	18		T5	47
valid_sources[0x36]	132935	1			T3	2		T4	25		T5	33
valid_sources[0x37]	127754	1			T3	506		T4	21		T5	36
valid_sources[0x38]	136204	1			T3	1		T4	40		T5	48
valid_sources[0x39]	135355	1			T4	15		T5	30		T6	97
valid_sources[0x3a]	131104	1			T3	1		T4	19		T5	31
valid_sources[0x3b]	134812	1			T3	2		T4	19		T5	53
valid_sources[0x3c]	120359	1			T4	22		T5	29		T6	102
valid_sources[0x3d]	124327	1			T3	508		T4	22		T5	35
valid_sources[0x3e]	129967	1			T3	511		T4	19		T5	31
valid_sources[0x3f]	126121	1			T1	1		T4	23		T5	29
valid_sources[0x40]	135800	1			T4	14		T5	46		T6	115
valid_sources[0x41]	134535	1			T3	1		T4	9		T5	18
valid_sources[0x42]	129871	1			T3	1		T4	28		T5	22
valid_sources[0x43]	144160	1			T3	509		T4	39		T5	44
valid_sources[0x44]	131461	1			T3	506		T4	15		T5	25
valid_sources[0x45]	131687	1			T3	1		T4	35		T5	22
valid_sources[0x46]	120298	1			T4	19		T5	39		T6	96
valid_sources[0x47]	122493	1			T3	2		T4	35		T5	36
valid_sources[0x48]	126061	1			T3	13		T4	11		T5	31
valid_sources[0x49]	142011	1			T3	504		T4	36		T5	25
valid_sources[0x4a]	127801	1			T3	2		T4	18		T5	35
valid_sources[0x4b]	139051	1			T3	2		T4	17		T5	28
valid_sources[0x4c]	136982	1			T3	503		T4	15		T5	35
valid_sources[0x4d]	125574	1			T3	2		T4	23		T5	26
valid_sources[0x4e]	121698	1			T2	8		T3	6		T4	34
valid_sources[0x4f]	123385	1			T4	32		T5	37		T6	99
valid_sources[0x50]	124204	1			T3	2		T4	18		T5	42
valid_sources[0x51]	136430	1			T4	10		T5	36		T6	104
valid_sources[0x52]	115714	1			T3	1		T4	12		T5	34
valid_sources[0x53]	132330	1			T3	1		T4	14		T5	44
valid_sources[0x54]	150527	1			T3	1		T4	26		T5	31
valid_sources[0x55]	134170	1			T3	501		T4	25		T5	43
valid_sources[0x56]	123832	1			T3	4		T4	16		T5	30
valid_sources[0x57]	136295	1			T4	8		T5	55		T6	93
valid_sources[0x58]	152197	1			T4	6		T5	37		T6	88
valid_sources[0x59]	131124	1			T3	1		T4	24		T5	39
valid_sources[0x5a]	121901	1			T2	2		T3	2		T4	12
valid_sources[0x5b]	125302	1			T1	2		T3	502		T4	13
valid_sources[0x5c]	126217	1			T3	1		T4	5		T5	23
valid_sources[0x5d]	124551	1			T4	14		T5	26		T6	101
valid_sources[0x5e]	122388	1			T3	1		T4	16		T5	22
valid_sources[0x5f]	140998	1			T3	501		T4	9		T5	36
valid_sources[0x60]	124807	1			T3	2		T4	23		T5	29
valid_sources[0x61]	152331	1			T4	15		T5	19		T6	105
valid_sources[0x62]	140066	1			T4	20		T5	41		T6	90
valid_sources[0x63]	121758	1			T3	3		T4	24		T5	32
valid_sources[0x64]	142638	1			T4	17		T5	31		T6	96
valid_sources[0x65]	125151	1			T3	1		T4	10		T5	37
valid_sources[0x66]	127429	1			T4	8		T5	52		T6	89
valid_sources[0x67]	134495	1			T3	505		T4	21		T5	37
valid_sources[0x68]	129531	1			T3	2		T4	15		T5	36
valid_sources[0x69]	125014	1			T3	1		T4	17		T5	49
valid_sources[0x6a]	126598	1			T3	1		T4	21		T5	18
valid_sources[0x6b]	121646	1			T3	2		T4	20		T5	32
valid_sources[0x6c]	125045	1			T3	1		T4	26		T5	41
valid_sources[0x6d]	127250	1			T3	1		T4	12		T5	27
valid_sources[0x6e]	127342	1			T3	1		T4	14		T5	47
valid_sources[0x6f]	122724	1			T3	6		T4	20		T5	36
valid_sources[0x70]	126777	1			T3	508		T4	15		T5	24
valid_sources[0x71]	128751	1			T3	506		T4	13		T5	40
valid_sources[0x72]	131362	1			T4	9		T5	31		T6	110
valid_sources[0x73]	148322	1			T4	12		T5	21		T6	86
valid_sources[0x74]	128395	1			T3	2		T4	17		T5	32
valid_sources[0x75]	133392	1			T4	36		T5	41		T6	115
valid_sources[0x76]	132083	1			T3	2		T4	10		T5	33
valid_sources[0x77]	128349	1			T3	1		T4	7		T5	39
valid_sources[0x78]	133140	1			T3	2		T4	10		T5	41
valid_sources[0x79]	122969	1			T3	1		T4	7		T5	31
valid_sources[0x7a]	125476	1			T3	2		T4	15		T5	42
valid_sources[0x7b]	124524	1			T4	24		T5	56		T6	110
valid_sources[0x7c]	119896	1			T4	27		T5	46		T6	106
valid_sources[0x7d]	128466	1			T3	1		T4	6		T5	31
valid_sources[0x7e]	136044	1			T3	2		T4	7		T5	43
valid_sources[0x7f]	121303	1			T4	21		T5	29		T6	123
valid_sources[0x80]	141319	1			T3	522		T4	10		T5	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6470788

1

T1

1

T2

2

T3

2136

values[0x0]

all_enables

biggest_size

208013

1

T1

1

T2

7

T3

119

values[0x1]

all_enables

biggest_size

142995

1

T1

1

T2

6

T3

62