Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf	91.67	100.00	66.67			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	100.00	72.73			90.91	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	88.21	100.00	80.00			84.62

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T10,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T14
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	406079264	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	406079264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	406079264	0	0
T2	15624	22	0	0
T3	410868	67211	0	0
T4	236370	37284	0	0
T5	434364	3723	0	0
T6	1102638	3331	0	0
T7	578286	4791	0	0
T8	327684	6005	0	0
T9	94242	13138	0	0
T10	132304	14747	0	0
T14	1457236	725866	0	0
T15	0	64751	0	0
T16	0	645338	0	0
T17	0	467617	0	0
T19	0	9545	0	0
T22	0	82671	0	0
T30	0	37062	0	0
T31	0	188	0	0
T43	0	1205	0	0
T44	582616	48682	0	0
T45	31108	5988	0	0
T46	218344	62152	0	0
T53	105690	0	0	0
T55	1278640	0	0	0
T73	135028	0	0	0
T80	3758	0	0	0
T173	582444	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12872	12384	0	0
T2	31248	30640	0	0
T3	547824	547168	0	0
T4	315160	314672	0	0
T5	579152	578536	0	0
T6	1470184	1469752	0	0
T7	771048	770544	0	0
T8	436912	436224	0	0
T9	125656	125040	0	0
T10	132304	131896	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12872	12384	0	0
T2	31248	30640	0	0
T3	547824	547168	0	0
T4	315160	314672	0	0
T5	579152	578536	0	0
T6	1470184	1469752	0	0
T7	771048	770544	0	0
T8	436912	436224	0	0
T9	125656	125040	0	0
T10	132304	131896	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12872	12384	0	0
T2	31248	30640	0	0
T3	547824	547168	0	0
T4	315160	314672	0	0
T5	579152	578536	0	0
T6	1470184	1469752	0	0
T7	771048	770544	0	0
T8	436912	436224	0	0
T9	125656	125040	0	0
T10	132304	131896	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	406079264	0	0
T2	15624	22	0	0
T3	410868	67211	0	0
T4	236370	37284	0	0
T5	434364	3723	0	0
T6	1102638	3331	0	0
T7	578286	4791	0	0
T8	327684	6005	0	0
T9	94242	13138	0	0
T10	132304	14747	0	0
T14	1457236	725866	0	0
T15	0	64751	0	0
T16	0	645338	0	0
T17	0	467617	0	0
T19	0	9545	0	0
T22	0	82671	0	0
T30	0	37062	0	0
T31	0	188	0	0
T43	0	1205	0	0
T44	582616	48682	0	0
T45	31108	5988	0	0
T46	218344	62152	0	0
T53	105690	0	0	0
T55	1278640	0	0	0
T73	135028	0	0	0
T80	3758	0	0	0
T173	582444	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	16	66.67
Logical	24	16	66.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T14,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T14,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T14,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T14,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	201247	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	201247	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	201247	0	0
T10	16538	64	0	0
T14	728618	3	0	0
T15	0	186	0	0
T16	0	256	0	0
T17	0	276	0	0
T19	0	42	0	0
T22	0	139	0	0
T31	0	188	0	0
T32	0	1088	0	0
T43	0	1	0	0
T44	72827	0	0	0
T45	7777	0	0	0
T46	109172	0	0	0
T53	52845	0	0	0
T55	639320	0	0	0
T73	67514	0	0	0
T80	1879	0	0	0
T173	291222	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	201247	0	0
T10	16538	64	0	0
T14	728618	3	0	0
T15	0	186	0	0
T16	0	256	0	0
T17	0	276	0	0
T19	0	42	0	0
T22	0	139	0	0
T31	0	188	0	0
T32	0	1088	0	0
T43	0	1	0	0
T44	72827	0	0	0
T45	7777	0	0	0
T46	109172	0	0	0
T53	52845	0	0	0
T55	639320	0	0	0
T73	67514	0	0	0
T80	1879	0	0	0
T173	291222	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T165,T84
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T14

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T14

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T32,T165,T84
1	0	Covered	T3,T10,T14
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T10,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	203797	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	203797	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	203797	0	0
T3	68478	257	0	0
T4	39395	0	0	0
T5	72394	0	0	0
T6	183773	0	0	0
T7	96381	0	0	0
T8	54614	0	0	0
T9	15707	0	0	0
T10	16538	2	0	0
T14	0	775	0	0
T15	0	170	0	0
T16	0	25	0	0
T17	0	8	0	0
T19	0	43	0	0
T22	0	160	0	0
T30	0	186	0	0
T43	0	2	0	0
T44	72827	0	0	0
T45	7777	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	203797	0	0
T3	68478	257	0	0
T4	39395	0	0	0
T5	72394	0	0	0
T6	183773	0	0	0
T7	96381	0	0	0
T8	54614	0	0	0
T9	15707	0	0	0
T10	16538	2	0	0
T14	0	775	0	0
T15	0	170	0	0
T16	0	25	0	0
T17	0	8	0	0
T19	0	43	0	0
T22	0	160	0	0
T30	0	186	0	0
T43	0	2	0	0
T44	72827	0	0	0
T45	7777	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T73
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T73
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	159781	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	159781	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	159781	0	0
T2	3906	7	0	0
T3	68478	0	0	0
T4	39395	16	0	0
T5	72394	225	0	0
T6	183773	812	0	0
T7	96381	377	0	0
T8	54614	129	0	0
T9	15707	64	0	0
T10	16538	0	0	0
T44	72827	160	0	0
T45	0	33	0	0
T46	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	159781	0	0
T2	3906	7	0	0
T3	68478	0	0	0
T4	39395	16	0	0
T5	72394	225	0	0
T6	183773	812	0	0
T7	96381	377	0	0
T8	54614	129	0	0
T9	15707	64	0	0
T10	16538	0	0	0
T44	72827	160	0	0
T45	0	33	0	0
T46	0	210	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T55,T174,T184
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T55,T174,T184
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	319624	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	319624	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	319624	0	0
T2	3906	3	0	0
T3	68478	0	0	0
T4	39395	19	0	0
T5	72394	157	0	0
T6	183773	128	0	0
T7	96381	289	0	0
T8	54614	171	0	0
T9	15707	2	0	0
T10	16538	0	0	0
T44	72827	418	0	0
T45	0	2	0	0
T46	0	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	319624	0	0
T2	3906	3	0	0
T3	68478	0	0	0
T4	39395	19	0	0
T5	72394	157	0	0
T6	183773	128	0	0
T7	96381	289	0	0
T8	54614	171	0	0
T9	15707	2	0	0
T10	16538	0	0	0
T44	72827	418	0	0
T45	0	2	0	0
T46	0	333	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T10,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T14

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T14

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T14
1	0	Covered	T3,T10,T14
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T10,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	112743915	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	112743915	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	112743915	0	0
T3	68478	66954	0	0
T4	39395	0	0	0
T5	72394	0	0	0
T6	183773	0	0	0
T7	96381	0	0	0
T8	54614	0	0	0
T9	15707	0	0	0
T10	16538	14681	0	0
T14	0	725088	0	0
T15	0	64395	0	0
T16	0	645057	0	0
T17	0	467333	0	0
T19	0	9460	0	0
T22	0	82372	0	0
T30	0	36876	0	0
T43	0	1202	0	0
T44	72827	0	0	0
T45	7777	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	112743915	0	0
T3	68478	66954	0	0
T4	39395	0	0	0
T5	72394	0	0	0
T6	183773	0	0	0
T7	96381	0	0	0
T8	54614	0	0	0
T9	15707	0	0	0
T10	16538	14681	0	0
T14	0	725088	0	0
T15	0	64395	0	0
T16	0	645057	0	0
T17	0	467333	0	0
T19	0	9460	0	0
T22	0	82372	0	0
T30	0	36876	0	0
T43	0	1202	0	0
T44	72827	0	0	0
T45	7777	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T32,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T14,T16
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T32,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T14,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T14,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T14,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	26196413	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	26196413	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	26196413	0	0
T10	16538	14196	0	0
T14	728618	18	0	0
T15	0	7345	0	0
T16	0	1733	0	0
T17	0	8553	0	0
T19	0	277	0	0
T22	0	948	0	0
T31	0	1990	0	0
T32	0	220638	0	0
T43	0	8	0	0
T44	72827	0	0	0
T45	7777	0	0	0
T46	109172	0	0	0
T53	52845	0	0	0
T55	639320	0	0	0
T73	67514	0	0	0
T80	1879	0	0	0
T173	291222	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	26196413	0	0
T10	16538	14196	0	0
T14	728618	18	0	0
T15	0	7345	0	0
T16	0	1733	0	0
T17	0	8553	0	0
T19	0	277	0	0
T22	0	948	0	0
T31	0	1990	0	0
T32	0	220638	0	0
T43	0	8	0	0
T44	72827	0	0	0
T45	7777	0	0	0
T46	109172	0	0	0
T53	52845	0	0	0
T55	639320	0	0	0
T73	67514	0	0	0
T80	1879	0	0	0
T173	291222	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	32199856	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	32199856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	32199856	0	0
T2	3906	1611	0	0
T3	68478	0	0	0
T4	39395	34471	0	0
T5	72394	66530	0	0
T6	183773	166802	0	0
T7	96381	72828	0	0
T8	54614	40307	0	0
T9	15707	13219	0	0
T10	16538	0	0	0
T44	72827	21892	0	0
T45	0	6612	0	0
T46	0	43195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	32199856	0	0
T2	3906	1611	0	0
T3	68478	0	0	0
T4	39395	34471	0	0
T5	72394	66530	0	0
T6	183773	166802	0	0
T7	96381	72828	0	0
T8	54614	40307	0	0
T9	15707	13219	0	0
T10	16538	0	0	0
T44	72827	21892	0	0
T45	0	6612	0	0
T46	0	43195	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T185,T186,T187
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386623199	234054631	0	0
DepthKnown_A	386623199	386449403	0	0
RvalidKnown_A	386623199	386449403	0	0
WreadyKnown_A	386623199	386449403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	386623199	234054631	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	234054631	0	0
T2	3906	19	0	0
T3	68478	0	0	0
T4	39395	37265	0	0
T5	72394	3566	0	0
T6	183773	3203	0	0
T7	96381	4502	0	0
T8	54614	5834	0	0
T9	15707	13136	0	0
T10	16538	0	0	0
T44	72827	48264	0	0
T45	0	5986	0	0
T46	0	61819	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	386449403	0	0
T1	1609	1548	0	0
T2	3906	3830	0	0
T3	68478	68396	0	0
T4	39395	39334	0	0
T5	72394	72317	0	0
T6	183773	183719	0	0
T7	96381	96318	0	0
T8	54614	54528	0	0
T9	15707	15630	0	0
T10	16538	16487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	386623199	234054631	0	0
T2	3906	19	0	0
T3	68478	0	0	0
T4	39395	37265	0	0
T5	72394	3566	0	0
T6	183773	3203	0	0
T7	96381	4502	0	0
T8	54614	5834	0	0
T9	15707	13136	0	0
T10	16538	0	0	0
T44	72827	48264	0	0
T45	0	5986	0	0
T46	0	61819	0	0