Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	387256208	0	0	0
ctrl_rd_A	387256208	1837	0	0
host_fifo_config_rd_A	387256208	3426	0	0
host_nack_handler_timeout_rd_A	387256208	979	0	0
host_timeout_ctrl_rd_A	387256208	820	0	0
intr_enable_rd_A	387256208	3287	0	0
ovrd_rd_A	387256208	1983	0	0
target_fifo_config_rd_A	387256208	976	0	0
target_id_rd_A	387256208	1212	0	0
target_timeout_ctrl_rd_A	387256208	1028	0	0
timeout_ctrl_rd_A	387256208	1191	0	0
timing0_rd_A	387256208	927	0	0
timing1_rd_A	387256208	991	0	0
timing2_rd_A	387256208	949	0	0
timing3_rd_A	387256208	1018	0	0
timing4_rd_A	387256208	1013	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1837	0	0
T106	26369	213	0	0
T107	1757	34	0	0
T108	6849	77	0	0
T109	4809	22	0	0
T110	6024	63	0	0
T111	1830	37	0	0
T112	13412	76	0	0
T113	3132	6	0	0
T114	1504	5	0	0
T115	1965	20	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	3426	0	0
T116	409006	172	0	0
T117	493605	164	0	0
T118	0	148	0	0
T119	0	183	0	0
T120	0	160	0	0
T121	0	226	0	0
T122	0	84	0	0
T123	0	122	0	0
T124	0	99	0	0
T125	0	221	0	0
T126	1178	0	0	0
T127	116199	0	0	0
T128	18688	0	0	0
T129	88466	0	0	0
T130	10039	0	0	0
T131	13891	0	0	0
T132	13052	0	0	0
T133	8477	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	979	0	0
T106	26369	216	0	0
T107	1757	15	0	0
T108	6849	23	0	0
T109	4809	37	0	0
T110	6024	45	0	0
T111	1830	2	0	0
T112	13412	24	0	0
T113	3132	31	0	0
T134	5982	3	0	0
T135	3458	22	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	820	0	0
T106	26369	198	0	0
T107	1757	7	0	0
T108	6849	37	0	0
T109	4809	22	0	0
T110	6024	52	0	0
T112	13412	40	0	0
T113	3132	35	0	0
T114	1504	1	0	0
T134	5982	7	0	0
T135	3458	40	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	3287	0	0
T106	0	253	0	0
T107	0	6	0	0
T108	0	78	0	0
T109	0	14	0	0
T136	230307	16	0	0
T137	0	60	0	0
T138	0	3	0	0
T139	0	16	0	0
T140	0	15	0	0
T141	0	4	0	0
T142	35852	0	0	0
T143	60414	0	0	0
T144	7665	0	0	0
T145	94829	0	0	0
T146	57435	0	0	0
T147	179591	0	0	0
T148	13671	0	0	0
T149	105359	0	0	0
T150	16210	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1983	0	0
T23	24216	0	0	0
T32	459664	0	0	0
T41	157288	0	0	0
T69	451288	0	0	0
T82	1983	44	0	0
T101	2099	46	0	0
T151	0	47	0	0
T152	0	46	0	0
T153	0	56	0	0
T154	0	38	0	0
T155	0	31	0	0
T156	0	34	0	0
T157	0	45	0	0
T158	0	40	0	0
T159	115190	0	0	0
T160	12652	0	0	0
T161	93936	0	0	0
T162	22608	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	976	0	0
T106	26369	206	0	0
T107	1757	5	0	0
T108	6849	23	0	0
T109	4809	17	0	0
T110	6024	13	0	0
T111	1830	9	0	0
T112	13412	44	0	0
T113	3132	5	0	0
T134	5982	20	0	0
T135	3458	17	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1212	0	0
T106	26369	213	0	0
T107	1757	19	0	0
T108	6849	56	0	0
T110	6024	39	0	0
T112	13412	40	0	0
T113	3132	17	0	0
T114	1504	15	0	0
T134	5982	7	0	0
T135	3458	12	0	0
T163	1543	3	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1028	0	0
T106	26369	251	0	0
T107	1757	1	0	0
T108	6849	30	0	0
T109	4809	41	0	0
T110	6024	40	0	0
T111	1830	3	0	0
T112	13412	52	0	0
T134	5982	30	0	0
T135	3458	5	0	0
T163	1543	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1191	0	0
T106	26369	215	0	0
T107	1757	5	0	0
T108	6849	56	0	0
T109	4809	50	0	0
T110	6024	38	0	0
T112	13412	26	0	0
T113	3132	57	0	0
T134	5982	17	0	0
T135	3458	20	0	0
T163	1543	2	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	927	0	0
T106	26369	249	0	0
T107	1757	9	0	0
T108	6849	39	0	0
T109	4809	20	0	0
T110	6024	59	0	0
T112	13412	46	0	0
T113	3132	6	0	0
T134	5982	23	0	0
T135	3458	7	0	0
T163	1543	8	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	991	0	0
T106	26369	241	0	0
T107	1757	13	0	0
T108	6849	6	0	0
T109	4809	41	0	0
T110	6024	56	0	0
T111	1830	7	0	0
T112	13412	26	0	0
T134	5982	4	0	0
T135	3458	25	0	0
T163	1543	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	949	0	0
T106	26369	179	0	0
T107	1757	8	0	0
T108	6849	28	0	0
T109	4809	39	0	0
T110	6024	46	0	0
T111	1830	2	0	0
T112	13412	59	0	0
T113	3132	34	0	0
T135	3458	15	0	0
T163	1543	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1018	0	0
T106	26369	214	0	0
T107	1757	13	0	0
T108	6849	31	0	0
T109	4809	19	0	0
T110	6024	28	0	0
T112	13412	73	0	0
T113	3132	37	0	0
T134	5982	5	0	0
T135	3458	36	0	0
T163	1543	10	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387256208	1013	0	0
T106	26369	206	0	0
T107	1757	16	0	0
T108	6849	19	0	0
T109	4809	32	0	0
T110	6024	63	0	0
T112	13412	54	0	0
T113	3132	35	0	0
T134	5982	3	0	0
T135	3458	43	0	0
T163	1543	1	0	0