Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27006893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7779223

1

T1

207

T2

32

T3

84974

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34026274	1			T1	557		T2	34		T3	325826
values[0x0]	378637	1			T1	90		T2	49		T3	3227
values[0x1]	381205	1			T1	115		T2	30		T3	3176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18956655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15829461

1

T1

351

T2

49

T3

155790

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	141825	1			T3	1322		T4	1		T5	4
valid_sources[0x01]	112657	1			T1	3		T3	1334		T4	1
valid_sources[0x02]	150049	1			T1	4		T3	1303		T5	6
valid_sources[0x03]	137071	1			T3	1265		T5	3		T7	494
valid_sources[0x04]	131643	1			T1	8		T3	1317		T5	6
valid_sources[0x05]	142207	1			T1	1		T3	1288		T5	3
valid_sources[0x06]	146924	1			T1	1		T3	1237		T5	2
valid_sources[0x07]	129928	1			T1	3		T3	1286		T5	5
valid_sources[0x08]	128215	1			T1	4		T3	1255		T5	6
valid_sources[0x09]	122257	1			T1	13		T3	1318		T4	1
valid_sources[0x0a]	148854	1			T1	2		T3	1265		T5	3
valid_sources[0x0b]	132723	1			T1	3		T3	1281		T5	6
valid_sources[0x0c]	152660	1			T1	4		T3	1363		T4	1
valid_sources[0x0d]	140303	1			T1	3		T3	1252		T4	1
valid_sources[0x0e]	139352	1			T1	11		T3	1291		T5	2
valid_sources[0x0f]	132533	1			T3	1293		T5	1		T6	1
valid_sources[0x10]	129106	1			T1	7		T3	1288		T4	1
valid_sources[0x11]	133849	1			T1	2		T3	1235		T5	1
valid_sources[0x12]	151709	1			T3	1306		T5	5		T6	330
valid_sources[0x13]	121551	1			T1	6		T2	3		T3	1319
valid_sources[0x14]	131012	1			T1	1		T3	1325		T5	5
valid_sources[0x15]	126739	1			T1	3		T2	1		T3	1425
valid_sources[0x16]	136681	1			T1	1		T3	1266		T4	2
valid_sources[0x17]	132183	1			T1	4		T3	1282		T4	1
valid_sources[0x18]	127148	1			T3	1302		T4	1		T5	3
valid_sources[0x19]	136185	1			T1	2		T2	2		T3	1272
valid_sources[0x1a]	149358	1			T1	3		T2	1		T3	1307
valid_sources[0x1b]	132097	1			T1	1		T3	1348		T5	4
valid_sources[0x1c]	137679	1			T1	5		T3	1255		T5	3
valid_sources[0x1d]	159705	1			T1	5		T3	1274		T4	1
valid_sources[0x1e]	137144	1			T1	2		T3	1229		T5	1
valid_sources[0x1f]	146776	1			T3	1271		T4	1		T5	3
valid_sources[0x20]	130329	1			T1	1		T3	1242		T6	223
valid_sources[0x21]	135956	1			T1	5		T3	1258		T5	2
valid_sources[0x22]	123685	1			T3	1305		T5	2		T7	541
valid_sources[0x23]	155546	1			T1	5		T3	1375		T4	1
valid_sources[0x24]	120786	1			T1	2		T3	1276		T5	6
valid_sources[0x25]	125883	1			T1	4		T3	1288		T5	4
valid_sources[0x26]	124632	1			T1	1		T3	1281		T5	2
valid_sources[0x27]	151179	1			T1	7		T2	2		T3	1312
valid_sources[0x28]	121999	1			T1	12		T2	5		T3	1304
valid_sources[0x29]	141869	1			T1	7		T2	1		T3	1296
valid_sources[0x2a]	127994	1			T3	1294		T4	1		T5	1
valid_sources[0x2b]	121766	1			T1	6		T3	1345		T5	3
valid_sources[0x2c]	138733	1			T1	1		T3	1320		T5	4
valid_sources[0x2d]	138878	1			T3	1299		T5	5		T6	84
valid_sources[0x2e]	122338	1			T1	10		T3	1317		T5	3
valid_sources[0x2f]	141318	1			T3	1305		T5	3		T7	599
valid_sources[0x30]	148739	1			T3	1338		T4	1		T5	8
valid_sources[0x31]	147886	1			T1	1		T3	1370		T5	4
valid_sources[0x32]	146427	1			T1	5		T2	2		T3	1263
valid_sources[0x33]	127438	1			T1	2		T2	4		T3	1294
valid_sources[0x34]	128162	1			T3	1268		T5	2		T7	523
valid_sources[0x35]	128039	1			T1	7		T3	1272		T5	4
valid_sources[0x36]	112022	1			T1	2		T3	1318		T4	1
valid_sources[0x37]	151354	1			T3	1269		T5	5		T6	1
valid_sources[0x38]	124492	1			T3	1294		T5	3		T7	600
valid_sources[0x39]	134740	1			T1	6		T3	1259		T5	3
valid_sources[0x3a]	117073	1			T1	3		T3	1222		T5	1
valid_sources[0x3b]	138980	1			T3	1306		T5	6		T7	643
valid_sources[0x3c]	141386	1			T1	2		T3	1302		T4	1
valid_sources[0x3d]	127882	1			T1	6		T2	2		T3	1219
valid_sources[0x3e]	146218	1			T1	3		T2	2		T3	1281
valid_sources[0x3f]	128283	1			T1	5		T3	1356		T5	3
valid_sources[0x40]	143670	1			T1	2		T2	6		T3	1307
valid_sources[0x41]	124257	1			T1	1		T3	1251		T4	2
valid_sources[0x42]	122436	1			T1	9		T3	1243		T5	8
valid_sources[0x43]	138505	1			T1	2		T3	1304		T5	8
valid_sources[0x44]	153061	1			T1	2		T3	1358		T5	4
valid_sources[0x45]	127506	1			T1	3		T3	1306		T5	4
valid_sources[0x46]	152243	1			T3	1213		T5	4		T7	529
valid_sources[0x47]	128161	1			T1	5		T3	1304		T5	6
valid_sources[0x48]	143664	1			T1	2		T3	1313		T4	1
valid_sources[0x49]	140771	1			T1	1		T2	3		T3	1328
valid_sources[0x4a]	133731	1			T1	1		T3	1367		T5	8
valid_sources[0x4b]	147021	1			T1	3		T2	2		T3	1336
valid_sources[0x4c]	125926	1			T1	1		T3	1305		T5	4
valid_sources[0x4d]	140145	1			T1	4		T3	1288		T5	2
valid_sources[0x4e]	123480	1			T3	1350		T5	5		T7	536
valid_sources[0x4f]	133129	1			T1	6		T2	3		T3	1376
valid_sources[0x50]	120251	1			T1	3		T3	1218		T5	4
valid_sources[0x51]	132442	1			T1	8		T3	1312		T5	1
valid_sources[0x52]	143152	1			T1	9		T3	1255		T5	4
valid_sources[0x53]	135142	1			T1	6		T3	1268		T5	6
valid_sources[0x54]	128261	1			T1	7		T3	1341		T5	4
valid_sources[0x55]	119871	1			T1	1		T3	1188		T4	1
valid_sources[0x56]	159457	1			T1	4		T2	6		T3	1348
valid_sources[0x57]	137097	1			T1	1		T3	1364		T5	2
valid_sources[0x58]	126861	1			T3	1240		T4	1		T5	4
valid_sources[0x59]	116197	1			T2	3		T3	1290		T5	4
valid_sources[0x5a]	131381	1			T3	1385		T4	1		T5	8
valid_sources[0x5b]	140960	1			T3	1285		T4	1		T5	7
valid_sources[0x5c]	119397	1			T1	2		T3	1273		T5	4
valid_sources[0x5d]	135089	1			T1	6		T3	1259		T5	5
valid_sources[0x5e]	178353	1			T1	8		T3	1328		T5	5
valid_sources[0x5f]	152621	1			T1	6		T3	1307		T4	2
valid_sources[0x60]	131604	1			T1	2		T3	1316		T5	3
valid_sources[0x61]	130882	1			T3	1323		T5	3		T6	106
valid_sources[0x62]	133737	1			T1	3		T3	1210		T5	3
valid_sources[0x63]	158157	1			T1	3		T3	1314		T5	3
valid_sources[0x64]	120589	1			T1	3		T3	1286		T5	2
valid_sources[0x65]	148349	1			T2	3		T3	1437		T5	3
valid_sources[0x66]	123706	1			T1	1		T3	1302		T5	2
valid_sources[0x67]	125557	1			T1	1		T3	1284		T4	2
valid_sources[0x68]	130021	1			T1	10		T2	2		T3	1286
valid_sources[0x69]	137851	1			T1	1		T2	6		T3	1280
valid_sources[0x6a]	150992	1			T3	1345		T4	1		T5	4
valid_sources[0x6b]	137611	1			T3	1359		T5	3		T7	494
valid_sources[0x6c]	125031	1			T1	4		T3	1315		T5	4
valid_sources[0x6d]	125933	1			T1	3		T3	1304		T5	1
valid_sources[0x6e]	137078	1			T3	1302		T5	6		T6	124
valid_sources[0x6f]	127200	1			T1	2		T3	1255		T5	5
valid_sources[0x70]	140285	1			T3	1243		T5	7		T6	1
valid_sources[0x71]	140902	1			T1	6		T3	1316		T5	10
valid_sources[0x72]	148830	1			T1	6		T3	1229		T5	3
valid_sources[0x73]	136230	1			T1	3		T3	1263		T4	1
valid_sources[0x74]	145641	1			T1	5		T3	1338		T4	1
valid_sources[0x75]	163280	1			T1	4		T3	1274		T5	5
valid_sources[0x76]	143451	1			T3	1258		T4	1		T5	3
valid_sources[0x77]	144905	1			T1	2		T3	1343		T5	7
valid_sources[0x78]	137881	1			T1	3		T3	1263		T5	4
valid_sources[0x79]	129727	1			T1	3		T2	4		T3	1262
valid_sources[0x7a]	117244	1			T1	8		T3	1279		T4	1
valid_sources[0x7b]	166872	1			T3	1299		T4	1		T5	3
valid_sources[0x7c]	135786	1			T1	1		T3	1344		T4	1
valid_sources[0x7d]	129625	1			T1	3		T3	1271		T7	481
valid_sources[0x7e]	146414	1			T1	1		T3	1255		T5	5
valid_sources[0x7f]	130173	1			T1	2		T3	1348		T4	1
valid_sources[0x80]	138503	1			T3	1332		T4	2		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7438191

1

T1

138

T2

6

T3

82748

values[0x0]

all_enables

biggest_size

201098

1

T1

45

T2

19

T3

1506

values[0x1]

all_enables

biggest_size

139934

1

T1

24

T2

7

T3

720