Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	378295274	0	0	0
ctrl_rd_A	378295274	2537	0	0
host_fifo_config_rd_A	378295274	4684	0	0
host_nack_handler_timeout_rd_A	378295274	1308	0	0
host_timeout_ctrl_rd_A	378295274	1096	0	0
intr_enable_rd_A	378295274	4385	0	0
ovrd_rd_A	378295274	2284	0	0
target_fifo_config_rd_A	378295274	1375	0	0
target_id_rd_A	378295274	1757	0	0
target_timeout_ctrl_rd_A	378295274	1432	0	0
timeout_ctrl_rd_A	378295274	1616	0	0
timing0_rd_A	378295274	1443	0	0
timing1_rd_A	378295274	1429	0	0
timing2_rd_A	378295274	1423	0	0
timing3_rd_A	378295274	1307	0	0
timing4_rd_A	378295274	1400	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	2537	0	0
T92	2898	29	0	0
T93	2861	95	0	0
T94	11860	11	0	0
T95	2320	37	0	0
T96	7169	110	0	0
T97	3981	21	0	0
T98	7324	199	0	0
T99	3106	35	0	0
T100	2234	3	0	0
T101	13057	361	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	4684	0	0
T49	174953	0	0	0
T102	263665	96	0	0
T103	0	86	0	0
T104	0	144	0	0
T105	0	167	0	0
T106	0	215	0	0
T107	0	113	0	0
T108	0	203	0	0
T109	0	179	0	0
T110	0	261	0	0
T111	0	131	0	0
T112	312930	0	0	0
T113	36691	0	0	0
T114	13215	0	0	0
T115	47180	0	0	0
T116	32518	0	0	0
T117	442006	0	0	0
T118	141356	0	0	0
T119	97282	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1308	0	0
T92	2898	15	0	0
T93	2861	15	0	0
T94	11860	5	0	0
T95	2320	17	0	0
T96	7169	40	0	0
T97	3981	5	0	0
T98	7324	42	0	0
T99	3106	15	0	0
T101	13057	112	0	0
T120	7509	20	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1096	0	0
T92	2898	14	0	0
T93	2861	11	0	0
T94	11860	13	0	0
T95	2320	11	0	0
T96	7169	9	0	0
T97	3981	6	0	0
T98	7324	33	0	0
T99	3106	23	0	0
T100	2234	12	0	0
T120	7509	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	4385	0	0
T37	156387	0	0	0
T92	0	61	0	0
T93	0	17	0	0
T94	0	32	0	0
T95	0	9	0	0
T96	0	140	0	0
T97	0	16	0	0
T98	0	472	0	0
T109	145384	10	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	58834	0	0	0
T124	38155	0	0	0
T125	85585	0	0	0
T126	123164	0	0	0
T127	98078	0	0	0
T128	22342	0	0	0
T129	14630	0	0	0
T130	27451	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	2284	0	0
T76	1265	40	0	0
T131	1023	30	0	0
T132	0	51	0	0
T133	0	33	0	0
T134	0	75	0	0
T135	0	52	0	0
T136	0	27	0	0
T137	0	29	0	0
T138	0	38	0	0
T139	0	38	0	0
T140	37095	0	0	0
T141	18315	0	0	0
T142	141951	0	0	0
T143	169593	0	0	0
T144	77704	0	0	0
T145	76241	0	0	0
T146	15732	0	0	0
T147	997316	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1375	0	0
T92	2898	11	0	0
T93	2861	39	0	0
T94	11860	19	0	0
T95	2320	13	0	0
T96	7169	41	0	0
T97	3981	42	0	0
T98	7324	67	0	0
T99	3106	13	0	0
T100	2234	7	0	0
T120	7509	29	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1757	0	0
T92	2898	2	0	0
T93	2861	37	0	0
T94	11860	15	0	0
T95	2320	12	0	0
T96	7169	25	0	0
T97	3981	12	0	0
T98	7324	96	0	0
T99	3106	24	0	0
T101	13057	197	0	0
T120	7509	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1432	0	0
T93	2861	19	0	0
T94	11860	8	0	0
T95	2320	24	0	0
T96	7169	28	0	0
T97	3981	46	0	0
T98	7324	68	0	0
T99	3106	27	0	0
T100	2234	8	0	0
T101	13057	114	0	0
T120	7509	29	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1616	0	0
T92	2898	19	0	0
T93	2861	11	0	0
T94	11860	16	0	0
T95	2320	9	0	0
T96	7169	51	0	0
T97	3981	1	0	0
T98	7324	108	0	0
T99	3106	21	0	0
T101	13057	194	0	0
T120	7509	14	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1443	0	0
T92	2898	7	0	0
T93	2861	31	0	0
T94	11860	9	0	0
T95	2320	12	0	0
T96	7169	32	0	0
T97	3981	14	0	0
T98	7324	64	0	0
T99	3106	21	0	0
T101	13057	122	0	0
T120	7509	20	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1429	0	0
T92	2898	12	0	0
T93	2861	28	0	0
T94	11860	14	0	0
T95	2320	12	0	0
T96	7169	24	0	0
T97	3981	30	0	0
T98	7324	53	0	0
T99	3106	33	0	0
T100	2234	4	0	0
T120	7509	36	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1423	0	0
T92	2898	14	0	0
T93	2861	28	0	0
T94	11860	15	0	0
T95	2320	17	0	0
T96	7169	36	0	0
T97	3981	29	0	0
T98	7324	57	0	0
T99	3106	29	0	0
T100	2234	4	0	0
T120	7509	13	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1307	0	0
T92	2898	16	0	0
T93	2861	15	0	0
T94	11860	9	0	0
T95	2320	6	0	0
T96	7169	15	0	0
T97	3981	11	0	0
T98	7324	67	0	0
T99	3106	36	0	0
T100	2234	4	0	0
T120	7509	32	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378295274	1400	0	0
T92	2898	15	0	0
T93	2861	13	0	0
T94	11860	25	0	0
T95	2320	13	0	0
T96	7169	44	0	0
T97	3981	19	0	0
T98	7324	37	0	0
T99	3106	22	0	0
T101	13057	123	0	0
T120	7509	11	0	0