Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339	1			T1	8		T3	8		T6	1
all_values[1]	339	1			T1	8		T3	8		T6	1
all_values[2]	339	1			T1	8		T3	8		T6	1
all_values[3]	339	1			T1	8		T3	8		T6	1
all_values[4]	339	1			T1	8		T3	8		T6	1
all_values[5]	339	1			T1	8		T3	8		T6	1
all_values[6]	339	1			T1	8		T3	8		T6	1
all_values[7]	339	1			T1	8		T3	8		T6	1
all_values[8]	339	1			T1	8		T3	8		T6	1
all_values[9]	339	1			T1	8		T3	8		T6	1
all_values[10]	339	1			T1	8		T3	8		T6	1
all_values[11]	339	1			T1	8		T3	8		T6	1
all_values[12]	339	1			T1	8		T3	8		T6	1
all_values[13]	339	1			T1	8		T3	8		T6	1
all_values[14]	339	1			T1	8		T3	8		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3348

1

T1

62

T3

78

T6

15

auto[1]

1737

1

T1

58

T3

42

T11

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T1

11

T3

12

T6

15

auto[1]

4004

1

T1

109

T3

108

T11

60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	57	1			T1	1		T3	1		T6	1
all_values[0]	auto[0]	auto[1]	175	1			T1	3		T3	4		T11	3
all_values[0]	auto[1]	auto[1]	107	1			T1	4		T3	3		T11	2
all_values[1]	auto[0]	auto[0]	56	1			T6	1		T13	1		T14	1
all_values[1]	auto[0]	auto[1]	166	1			T1	4		T3	5		T11	3
all_values[1]	auto[1]	auto[1]	117	1			T1	4		T3	3		T11	2
all_values[2]	auto[0]	auto[0]	66	1			T6	1		T13	1		T14	1
all_values[2]	auto[0]	auto[1]	156	1			T1	2		T3	5		T11	3
all_values[2]	auto[1]	auto[1]	117	1			T1	6		T3	3		T11	2
all_values[3]	auto[0]	auto[0]	65	1			T6	1		T13	1		T14	1
all_values[3]	auto[0]	auto[1]	155	1			T1	3		T3	5		T11	1
all_values[3]	auto[1]	auto[1]	119	1			T1	5		T3	3		T11	2
all_values[4]	auto[0]	auto[0]	65	1			T6	1		T13	1		T14	1
all_values[4]	auto[0]	auto[1]	168	1			T1	4		T3	5		T11	4
all_values[4]	auto[1]	auto[1]	106	1			T1	4		T3	3		T11	1
all_values[5]	auto[0]	auto[0]	68	1			T1	2		T3	1		T6	1
all_values[5]	auto[0]	auto[1]	164	1			T1	3		T3	5		T11	1
all_values[5]	auto[1]	auto[1]	107	1			T1	3		T3	2		T11	3
all_values[6]	auto[0]	auto[0]	84	1			T1	4		T3	1		T6	1
all_values[6]	auto[0]	auto[1]	130	1			T1	1		T3	2		T11	3
all_values[6]	auto[1]	auto[1]	125	1			T1	3		T3	5		T11	1
all_values[7]	auto[0]	auto[0]	61	1			T6	1		T13	1		T14	1
all_values[7]	auto[0]	auto[1]	145	1			T1	5		T3	3		T11	1
all_values[7]	auto[1]	auto[1]	133	1			T1	3		T3	5		T11	4
all_values[8]	auto[0]	auto[0]	91	1			T6	1		T13	1		T14	1
all_values[8]	auto[0]	auto[1]	131	1			T1	3		T3	6		T11	1
all_values[8]	auto[1]	auto[1]	117	1			T1	5		T3	2		T11	4
all_values[9]	auto[0]	auto[0]	83	1			T1	2		T6	1		T13	1
all_values[9]	auto[0]	auto[1]	126	1			T1	5		T3	3		T11	1
all_values[9]	auto[1]	auto[1]	130	1			T1	1		T3	5		T11	2
all_values[10]	auto[0]	auto[0]	83	1			T1	1		T3	1		T6	1
all_values[10]	auto[0]	auto[1]	142	1			T1	3		T3	5		T11	2
all_values[10]	auto[1]	auto[1]	114	1			T1	4		T3	2		T11	1
all_values[11]	auto[0]	auto[0]	65	1			T3	3		T6	1		T13	1
all_values[11]	auto[0]	auto[1]	158	1			T1	3		T3	3		T11	4
all_values[11]	auto[1]	auto[1]	116	1			T1	5		T3	2		T11	1
all_values[12]	auto[0]	auto[0]	78	1			T1	1		T6	1		T13	1
all_values[12]	auto[0]	auto[1]	167	1			T1	4		T3	6		T11	2
all_values[12]	auto[1]	auto[1]	94	1			T1	3		T3	2		T11	1
all_values[13]	auto[0]	auto[0]	76	1			T3	1		T6	1		T13	1
all_values[13]	auto[0]	auto[1]	154	1			T1	4		T3	5		T12	5
all_values[13]	auto[1]	auto[1]	109	1			T1	4		T3	2		T48	2
all_values[14]	auto[0]	auto[0]	83	1			T3	4		T6	1		T13	1
all_values[14]	auto[0]	auto[1]	130	1			T1	4		T3	4		T11	3
all_values[14]	auto[1]	auto[1]	126	1			T1	4		T11	2		T12	6