Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
52.72 40.66 40.72 90.72 0.00 42.98 99.68 54.32


Total tests in report: 165
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
43.91 43.91 39.31 39.31 36.77 36.77 87.97 87.97 0.00 0.00 41.49 41.49 91.08 91.08 10.74 10.74 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2023095146
49.32 5.41 40.50 1.19 38.95 2.18 92.80 4.84 0.00 0.00 42.62 1.13 92.36 1.27 38.00 27.26 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3165556200
51.12 1.80 40.53 0.03 40.05 1.09 92.80 0.00 0.00 0.00 42.70 0.07 96.82 4.46 44.95 6.95 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1039292003
52.13 1.01 40.62 0.09 40.05 0.00 96.28 3.47 0.00 0.00 42.91 0.21 98.73 1.91 46.32 1.37 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.826247283
52.59 0.46 40.66 0.03 40.31 0.26 97.02 0.74 0.00 0.00 42.98 0.07 98.73 0.00 48.42 2.11 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2587949650
52.89 0.30 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 98.73 0.00 50.53 2.11 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3219124138
53.02 0.14 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.36 0.64 50.84 0.32 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1449072998
53.16 0.14 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.32 51.47 0.63 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2597575369
53.30 0.14 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.42 0.95 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2877426605
53.37 0.08 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.95 0.53 /workspace/coverage/cover_reg_top/3.i2c_intr_test.4276372591
53.45 0.08 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.47 0.53 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1321510861
53.51 0.06 40.66 0.00 40.53 0.23 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.68 0.21 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2569256785
53.54 0.03 40.66 0.00 40.53 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.21 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2391243135
53.57 0.03 40.66 0.00 40.53 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.11 0.21 /workspace/coverage/cover_reg_top/15.i2c_intr_test.703029989
53.59 0.02 40.66 0.00 40.57 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.21 0.11 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.606878624
53.60 0.02 40.66 0.00 40.57 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.32 0.11 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2011079847
53.61 0.01 40.66 0.00 40.65 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.32 0.00 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1046679881
53.62 0.01 40.66 0.00 40.68 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.32 0.00 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.974627727
53.63 0.01 40.66 0.00 40.72 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.32 0.00 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3327823997

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1897871338
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2385321548
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.233896054
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2597499349
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1410287860
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2802699475
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.122510221
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1198807054
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1306998003
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2769888152
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.193386008
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2966879428
/workspace/coverage/cover_reg_top/1.i2c_intr_test.3357134533
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.217125262
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3554879951
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2806689933
/workspace/coverage/cover_reg_top/10.i2c_intr_test.4094563742
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3039731684
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2808014340
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.203675974
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3535485563
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3117176897
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.457049752
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.3941535960
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1523755146
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794134392
/workspace/coverage/cover_reg_top/12.i2c_intr_test.3021185884
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2244265555
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1479294449
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4186435787
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3535122939
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2723461550
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2517944183
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.121390751
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3529366689
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1689318572
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1637524985
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.2419688277
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3002163099
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3912277942
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1685912915
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.705459689
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3798717082
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2630589555
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3347920883
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2160741349
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2513209311
/workspace/coverage/cover_reg_top/16.i2c_intr_test.3538962507
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3939528871
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.3858989795
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1173510766
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.3145901722
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2787427635
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.781189845
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.767901275
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3553206869
/workspace/coverage/cover_reg_top/18.i2c_intr_test.1655454878
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.812489652
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2567857558
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.292944750
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2460657318
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1701649460
/workspace/coverage/cover_reg_top/19.i2c_intr_test.3417813545
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.908737528
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.1803498831
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1017393095
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.633783636
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.73138018
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2613617784
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3137544528
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1019705569
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2199939428
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3327141324
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2936132064
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2296800190
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3265285376
/workspace/coverage/cover_reg_top/21.i2c_intr_test.4107971361
/workspace/coverage/cover_reg_top/22.i2c_intr_test.5431703
/workspace/coverage/cover_reg_top/23.i2c_intr_test.2982753139
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1644172321
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3236680084
/workspace/coverage/cover_reg_top/26.i2c_intr_test.224511346
/workspace/coverage/cover_reg_top/27.i2c_intr_test.350212811
/workspace/coverage/cover_reg_top/28.i2c_intr_test.899505154
/workspace/coverage/cover_reg_top/29.i2c_intr_test.70207310
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2704806973
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1399816404
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1807740327
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3558113285
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.163852174
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.996226102
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.432975189
/workspace/coverage/cover_reg_top/30.i2c_intr_test.1634872182
/workspace/coverage/cover_reg_top/31.i2c_intr_test.2571171314
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3060741437
/workspace/coverage/cover_reg_top/33.i2c_intr_test.1897504577
/workspace/coverage/cover_reg_top/34.i2c_intr_test.2141680144
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2929277578
/workspace/coverage/cover_reg_top/36.i2c_intr_test.1659698518
/workspace/coverage/cover_reg_top/38.i2c_intr_test.2316323003
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3560059032
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2884707623
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3143287006
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.993462109
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2249374213
/workspace/coverage/cover_reg_top/4.i2c_intr_test.1727602324
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3651184136
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.199352301
/workspace/coverage/cover_reg_top/41.i2c_intr_test.3855960011
/workspace/coverage/cover_reg_top/42.i2c_intr_test.495148493
/workspace/coverage/cover_reg_top/43.i2c_intr_test.2828540473
/workspace/coverage/cover_reg_top/44.i2c_intr_test.555313037
/workspace/coverage/cover_reg_top/45.i2c_intr_test.612063642
/workspace/coverage/cover_reg_top/46.i2c_intr_test.4129934412
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1172587601
/workspace/coverage/cover_reg_top/48.i2c_intr_test.1487763775
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2977233946
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3263491374
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.987582645
/workspace/coverage/cover_reg_top/5.i2c_intr_test.3703291554
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3667627192
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1068092724
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1195734935
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2363242210
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.863831085
/workspace/coverage/cover_reg_top/6.i2c_intr_test.2400538094
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2718817516
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3716641566
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2085497405
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4233865002
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2543770971
/workspace/coverage/cover_reg_top/7.i2c_intr_test.39548824
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1391191408
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.967496053
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1013613180
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1298702007
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.1459965340
/workspace/coverage/cover_reg_top/8.i2c_intr_test.3745755791
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.473079384
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.748390978
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1687403891
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1171845298
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2169857675
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1325566037
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.1152045870
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2037750356



Total test records in report: 165
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3165556200 Aug 14 04:27:30 PM PDT 24 Aug 14 04:27:31 PM PDT 24 19228794 ps
T2 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2460657318 Aug 14 04:27:12 PM PDT 24 Aug 14 04:27:13 PM PDT 24 65052382 ps
T3 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2169857675 Aug 14 04:27:20 PM PDT 24 Aug 14 04:27:21 PM PDT 24 48071450 ps
T6 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.473079384 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:51 PM PDT 24 58540628 ps
T7 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2249374213 Aug 14 04:26:45 PM PDT 24 Aug 14 04:26:46 PM PDT 24 24381471 ps
T8 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1019705569 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:50 PM PDT 24 24175304 ps
T4 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.705459689 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:51 PM PDT 24 189874287 ps
T5 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2023095146 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:00 PM PDT 24 22072004 ps
T9 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2769888152 Aug 14 04:26:42 PM PDT 24 Aug 14 04:26:43 PM PDT 24 32888078 ps
T10 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.812489652 Aug 14 04:27:01 PM PDT 24 Aug 14 04:27:02 PM PDT 24 281797912 ps
T13 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2808014340 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:56 PM PDT 24 30419800 ps
T19 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.826247283 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:53 PM PDT 24 92196953 ps
T20 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2597575369 Aug 14 04:27:18 PM PDT 24 Aug 14 04:27:19 PM PDT 24 67178963 ps
T14 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1039292003 Aug 14 04:27:05 PM PDT 24 Aug 14 04:27:07 PM PDT 24 119182404 ps
T23 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2630589555 Aug 14 04:27:15 PM PDT 24 Aug 14 04:27:16 PM PDT 24 203780335 ps
T11 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1897504577 Aug 14 04:27:07 PM PDT 24 Aug 14 04:27:07 PM PDT 24 42462232 ps
T24 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3667627192 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 39622951 ps
T12 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2400538094 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:50 PM PDT 24 17672974 ps
T25 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2513209311 Aug 14 04:27:15 PM PDT 24 Aug 14 04:27:16 PM PDT 24 68738503 ps
T29 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.633783636 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:52 PM PDT 24 56486694 ps
T26 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.457049752 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:51 PM PDT 24 170355147 ps
T47 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3039731684 Aug 14 04:27:11 PM PDT 24 Aug 14 04:27:12 PM PDT 24 115901436 ps
T27 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2385321548 Aug 14 04:27:01 PM PDT 24 Aug 14 04:27:04 PM PDT 24 209711043 ps
T15 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3529366689 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:01 PM PDT 24 39149951 ps
T48 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2517944183 Aug 14 04:27:00 PM PDT 24 Aug 14 04:27:00 PM PDT 24 45555223 ps
T21 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2587949650 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:57 PM PDT 24 129483680 ps
T49 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1655454878 Aug 14 04:27:00 PM PDT 24 Aug 14 04:27:01 PM PDT 24 43652021 ps
T50 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2877426605 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:04 PM PDT 24 114019757 ps
T28 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.987582645 Aug 14 04:26:57 PM PDT 24 Aug 14 04:26:58 PM PDT 24 95769064 ps
T37 /workspace/coverage/cover_reg_top/7.i2c_intr_test.39548824 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:04 PM PDT 24 42473995 ps
T38 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3002163099 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:55 PM PDT 24 20886201 ps
T16 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1013613180 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:51 PM PDT 24 150168520 ps
T39 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3219124138 Aug 14 04:27:16 PM PDT 24 Aug 14 04:27:16 PM PDT 24 36913272 ps
T40 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2929277578 Aug 14 04:27:17 PM PDT 24 Aug 14 04:27:18 PM PDT 24 20489826 ps
T41 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2419688277 Aug 14 04:26:54 PM PDT 24 Aug 14 04:26:55 PM PDT 24 83339124 ps
T42 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3236680084 Aug 14 04:27:00 PM PDT 24 Aug 14 04:27:01 PM PDT 24 20358360 ps
T43 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2704806973 Aug 14 04:26:53 PM PDT 24 Aug 14 04:26:54 PM PDT 24 125123466 ps
T17 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.432975189 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:52 PM PDT 24 261095666 ps
T22 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2569256785 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:54 PM PDT 24 490650831 ps
T69 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2718817516 Aug 14 04:27:06 PM PDT 24 Aug 14 04:27:07 PM PDT 24 22795161 ps
T30 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.863831085 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:56 PM PDT 24 17953147 ps
T79 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2982753139 Aug 14 04:27:17 PM PDT 24 Aug 14 04:27:18 PM PDT 24 28225326 ps
T18 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3558113285 Aug 14 04:26:43 PM PDT 24 Aug 14 04:26:44 PM PDT 24 34702608 ps
T82 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3538962507 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:10 PM PDT 24 16485915 ps
T84 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794134392 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:51 PM PDT 24 76940787 ps
T85 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3912277942 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:53 PM PDT 24 22559553 ps
T78 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2977233946 Aug 14 04:27:20 PM PDT 24 Aug 14 04:27:21 PM PDT 24 19385091 ps
T86 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1803498831 Aug 14 04:26:57 PM PDT 24 Aug 14 04:26:58 PM PDT 24 89274886 ps
T83 /workspace/coverage/cover_reg_top/28.i2c_intr_test.899505154 Aug 14 04:27:08 PM PDT 24 Aug 14 04:27:08 PM PDT 24 15753168 ps
T80 /workspace/coverage/cover_reg_top/3.i2c_intr_test.4276372591 Aug 14 04:26:46 PM PDT 24 Aug 14 04:26:47 PM PDT 24 21848346 ps
T31 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2884707623 Aug 14 04:26:57 PM PDT 24 Aug 14 04:27:01 PM PDT 24 114017526 ps
T87 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1523755146 Aug 14 04:26:53 PM PDT 24 Aug 14 04:26:55 PM PDT 24 172128721 ps
T32 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1449072998 Aug 14 04:27:04 PM PDT 24 Aug 14 04:27:05 PM PDT 24 22026059 ps
T77 /workspace/coverage/cover_reg_top/46.i2c_intr_test.4129934412 Aug 14 04:27:04 PM PDT 24 Aug 14 04:27:04 PM PDT 24 50154034 ps
T88 /workspace/coverage/cover_reg_top/44.i2c_intr_test.555313037 Aug 14 04:27:17 PM PDT 24 Aug 14 04:27:18 PM PDT 24 30615532 ps
T56 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.292944750 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:57 PM PDT 24 47142845 ps
T89 /workspace/coverage/cover_reg_top/27.i2c_intr_test.350212811 Aug 14 04:27:16 PM PDT 24 Aug 14 04:27:17 PM PDT 24 33448034 ps
T90 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3651184136 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:54 PM PDT 24 30340843 ps
T91 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3560059032 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:22 PM PDT 24 49001815 ps
T92 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1298702007 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:23 PM PDT 24 84403911 ps
T93 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3798717082 Aug 14 04:27:01 PM PDT 24 Aug 14 04:27:02 PM PDT 24 31888519 ps
T94 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2802699475 Aug 14 04:26:45 PM PDT 24 Aug 14 04:26:46 PM PDT 24 32496129 ps
T51 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1689318572 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:00 PM PDT 24 81992125 ps
T95 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3855960011 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 26624948 ps
T52 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.967496053 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:52 PM PDT 24 618829972 ps
T73 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2391243135 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:50 PM PDT 24 26644272 ps
T53 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2160741349 Aug 14 04:27:04 PM PDT 24 Aug 14 04:27:05 PM PDT 24 396076760 ps
T54 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.781189845 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:54 PM PDT 24 220349475 ps
T33 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2613617784 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:00 PM PDT 24 30612453 ps
T96 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.73138018 Aug 14 04:26:47 PM PDT 24 Aug 14 04:26:50 PM PDT 24 722413200 ps
T97 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1399816404 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:54 PM PDT 24 2507396915 ps
T98 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1644172321 Aug 14 04:27:19 PM PDT 24 Aug 14 04:27:20 PM PDT 24 27738544 ps
T99 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1171845298 Aug 14 04:27:13 PM PDT 24 Aug 14 04:27:13 PM PDT 24 44844702 ps
T60 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.199352301 Aug 14 04:26:56 PM PDT 24 Aug 14 04:27:02 PM PDT 24 78468134 ps
T72 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3327141324 Aug 14 04:26:39 PM PDT 24 Aug 14 04:26:40 PM PDT 24 34728740 ps
T100 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2787427635 Aug 14 04:26:56 PM PDT 24 Aug 14 04:26:57 PM PDT 24 76555027 ps
T101 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.193386008 Aug 14 04:26:41 PM PDT 24 Aug 14 04:26:42 PM PDT 24 117894989 ps
T102 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1637524985 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:00 PM PDT 24 264956401 ps
T68 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1321510861 Aug 14 04:27:02 PM PDT 24 Aug 14 04:27:03 PM PDT 24 26185115 ps
T103 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4233865002 Aug 14 04:26:46 PM PDT 24 Aug 14 04:26:47 PM PDT 24 81903322 ps
T65 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.203675974 Aug 14 04:26:48 PM PDT 24 Aug 14 04:26:50 PM PDT 24 58925940 ps
T104 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1325566037 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:12 PM PDT 24 110266132 ps
T105 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3716641566 Aug 14 04:26:57 PM PDT 24 Aug 14 04:26:59 PM PDT 24 124169618 ps
T106 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4107971361 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:10 PM PDT 24 21484399 ps
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T108 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2141680144 Aug 14 04:27:13 PM PDT 24 Aug 14 04:27:13 PM PDT 24 48605220 ps
T109 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1634872182 Aug 14 04:27:20 PM PDT 24 Aug 14 04:27:21 PM PDT 24 14629967 ps
T64 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4186435787 Aug 14 04:26:54 PM PDT 24 Aug 14 04:26:55 PM PDT 24 61226354 ps
T110 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3263491374 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 136001070 ps
T111 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3265285376 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:03 PM PDT 24 43024722 ps
T112 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2363242210 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 20636382 ps
T113 /workspace/coverage/cover_reg_top/42.i2c_intr_test.495148493 Aug 14 04:27:15 PM PDT 24 Aug 14 04:27:16 PM PDT 24 265695664 ps
T114 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.767901275 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:53 PM PDT 24 189930482 ps
T74 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1198807054 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:51 PM PDT 24 640108746 ps
T57 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2085497405 Aug 14 04:27:01 PM PDT 24 Aug 14 04:27:04 PM PDT 24 273249782 ps
T115 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3554879951 Aug 14 04:27:01 PM PDT 24 Aug 14 04:27:03 PM PDT 24 625307971 ps
T61 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.606878624 Aug 14 04:27:06 PM PDT 24 Aug 14 04:27:09 PM PDT 24 1349472956 ps
T116 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1410287860 Aug 14 04:26:45 PM PDT 24 Aug 14 04:26:46 PM PDT 24 32397730 ps
T67 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1017393095 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:54 PM PDT 24 282289654 ps
T117 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3145901722 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:11 PM PDT 24 55037076 ps
T58 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.974627727 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:00 PM PDT 24 71815460 ps
T75 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.121390751 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:04 PM PDT 24 117139078 ps
T118 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3858989795 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:53 PM PDT 24 86739306 ps
T62 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.122510221 Aug 14 04:26:53 PM PDT 24 Aug 14 04:26:55 PM PDT 24 152771515 ps
T63 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3327823997 Aug 14 04:27:07 PM PDT 24 Aug 14 04:27:09 PM PDT 24 69694200 ps
T119 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3535485563 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:52 PM PDT 24 78997162 ps
T120 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3060741437 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 38171408 ps
T121 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1897871338 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:51 PM PDT 24 28749336 ps
T122 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1487763775 Aug 14 04:27:07 PM PDT 24 Aug 14 04:27:08 PM PDT 24 17988366 ps
T123 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3021185884 Aug 14 04:26:54 PM PDT 24 Aug 14 04:26:54 PM PDT 24 41209643 ps
T124 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.233896054 Aug 14 04:26:48 PM PDT 24 Aug 14 04:26:50 PM PDT 24 33065804 ps
T125 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2936132064 Aug 14 04:26:42 PM PDT 24 Aug 14 04:26:43 PM PDT 24 74509683 ps
T126 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1173510766 Aug 14 04:27:08 PM PDT 24 Aug 14 04:27:09 PM PDT 24 70662010 ps
T127 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1479294449 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:01 PM PDT 24 152375093 ps
T128 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.993462109 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 29535044 ps
T129 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1172587601 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 17297003 ps
T76 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3143287006 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:49 PM PDT 24 28846944 ps
T130 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2316323003 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:23 PM PDT 24 111042174 ps
T131 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.748390978 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:50 PM PDT 24 301156671 ps
T34 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2723461550 Aug 14 04:27:06 PM PDT 24 Aug 14 04:27:07 PM PDT 24 28355324 ps
T132 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2567857558 Aug 14 04:27:08 PM PDT 24 Aug 14 04:27:11 PM PDT 24 92600240 ps
T133 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2597499349 Aug 14 04:26:48 PM PDT 24 Aug 14 04:26:49 PM PDT 24 178946723 ps
T134 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1152045870 Aug 14 04:26:58 PM PDT 24 Aug 14 04:27:00 PM PDT 24 55953407 ps
T135 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2828540473 Aug 14 04:27:19 PM PDT 24 Aug 14 04:27:20 PM PDT 24 18374323 ps
T136 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3117176897 Aug 14 04:26:52 PM PDT 24 Aug 14 04:26:53 PM PDT 24 24607623 ps
T137 /workspace/coverage/cover_reg_top/26.i2c_intr_test.224511346 Aug 14 04:27:11 PM PDT 24 Aug 14 04:27:11 PM PDT 24 16551716 ps
T138 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.217125262 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 591235371 ps
T139 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3745755791 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:04 PM PDT 24 75279780 ps
T140 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2011079847 Aug 14 04:27:14 PM PDT 24 Aug 14 04:27:15 PM PDT 24 67789541 ps
T141 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3535122939 Aug 14 04:27:00 PM PDT 24 Aug 14 04:27:02 PM PDT 24 34065900 ps
T142 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3941535960 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:12 PM PDT 24 475951775 ps
T143 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3137544528 Aug 14 04:26:46 PM PDT 24 Aug 14 04:26:47 PM PDT 24 44274307 ps
T144 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2571171314 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 19221743 ps
T145 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3347920883 Aug 14 04:27:19 PM PDT 24 Aug 14 04:27:21 PM PDT 24 109854176 ps
T146 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1687403891 Aug 14 04:26:50 PM PDT 24 Aug 14 04:26:51 PM PDT 24 116525901 ps
T35 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2806689933 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:49 PM PDT 24 43004602 ps
T147 /workspace/coverage/cover_reg_top/45.i2c_intr_test.612063642 Aug 14 04:27:15 PM PDT 24 Aug 14 04:27:15 PM PDT 24 23771871 ps
T148 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3417813545 Aug 14 04:27:19 PM PDT 24 Aug 14 04:27:19 PM PDT 24 156450201 ps
T55 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2296800190 Aug 14 04:26:46 PM PDT 24 Aug 14 04:26:47 PM PDT 24 127592523 ps
T36 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1807740327 Aug 14 04:26:53 PM PDT 24 Aug 14 04:26:59 PM PDT 24 88820019 ps
T149 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1459965340 Aug 14 04:27:11 PM PDT 24 Aug 14 04:27:12 PM PDT 24 188873218 ps
T150 /workspace/coverage/cover_reg_top/22.i2c_intr_test.5431703 Aug 14 04:27:03 PM PDT 24 Aug 14 04:27:04 PM PDT 24 19665745 ps
T70 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3939528871 Aug 14 04:26:59 PM PDT 24 Aug 14 04:27:01 PM PDT 24 124687446 ps
T151 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3357134533 Aug 14 04:26:55 PM PDT 24 Aug 14 04:26:56 PM PDT 24 34712208 ps
T152 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1195734935 Aug 14 04:26:47 PM PDT 24 Aug 14 04:26:49 PM PDT 24 153761811 ps
T153 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2966879428 Aug 14 04:26:51 PM PDT 24 Aug 14 04:26:52 PM PDT 24 36311535 ps
T154 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1068092724 Aug 14 04:26:47 PM PDT 24 Aug 14 04:26:49 PM PDT 24 206752286 ps
T155 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.996226102 Aug 14 04:27:02 PM PDT 24 Aug 14 04:27:03 PM PDT 24 50202876 ps
T156 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2037750356 Aug 14 04:27:05 PM PDT 24 Aug 14 04:27:06 PM PDT 24 54632495 ps
T157 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2543770971 Aug 14 04:27:30 PM PDT 24 Aug 14 04:27:31 PM PDT 24 74466715 ps
T46 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3553206869 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:10 PM PDT 24 21362450 ps
T158 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1727602324 Aug 14 04:26:54 PM PDT 24 Aug 14 04:26:55 PM PDT 24 28152499 ps
T159 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2244265555 Aug 14 04:26:49 PM PDT 24 Aug 14 04:26:50 PM PDT 24 57477961 ps
T160 /workspace/coverage/cover_reg_top/10.i2c_intr_test.4094563742 Aug 14 04:27:10 PM PDT 24 Aug 14 04:27:11 PM PDT 24 60175553 ps
T161 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1659698518 Aug 14 04:27:27 PM PDT 24 Aug 14 04:27:28 PM PDT 24 19239312 ps
T71 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.908737528 Aug 14 04:26:58 PM PDT 24 Aug 14 04:26:59 PM PDT 24 73368262 ps
T59 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1046679881 Aug 14 04:27:02 PM PDT 24 Aug 14 04:27:04 PM PDT 24 571809444 ps
T44 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1701649460 Aug 14 04:27:17 PM PDT 24 Aug 14 04:27:18 PM PDT 24 29421529 ps
T162 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1391191408 Aug 14 04:26:48 PM PDT 24 Aug 14 04:26:50 PM PDT 24 31482434 ps
T66 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1685912915 Aug 14 04:27:06 PM PDT 24 Aug 14 04:27:07 PM PDT 24 277600396 ps
T163 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3703291554 Aug 14 04:26:42 PM PDT 24 Aug 14 04:26:43 PM PDT 24 18114746 ps
T45 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1306998003 Aug 14 04:26:53 PM PDT 24 Aug 14 04:26:59 PM PDT 24 524841403 ps
T164 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.163852174 Aug 14 04:26:48 PM PDT 24 Aug 14 04:26:49 PM PDT 24 22539329 ps
T165 /workspace/coverage/cover_reg_top/29.i2c_intr_test.70207310 Aug 14 04:27:18 PM PDT 24 Aug 14 04:27:19 PM PDT 24 19010785 ps

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2023095146
Short name T5
Test name
Test status
Simulation time 22072004 ps
CPU time 0.86 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204504 kb
Host smart-88da57a4-4448-4743-afec-8ac7be7ed5c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023095146 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2023095146
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3165556200
Short name T1
Test name
Test status
Simulation time 19228794 ps
CPU time 0.7 seconds
Started Aug 14 04:27:30 PM PDT 24
Finished Aug 14 04:27:31 PM PDT 24
Peak memory 204664 kb
Host smart-7be84c30-f8ca-4aad-9ce9-aef46f057061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165556200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3165556200
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1039292003
Short name T14
Test name
Test status
Simulation time 119182404 ps
CPU time 2.22 seconds
Started Aug 14 04:27:05 PM PDT 24
Finished Aug 14 04:27:07 PM PDT 24
Peak memory 204700 kb
Host smart-f6639ba1-6fd0-4c47-a379-60d60619e83b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039292003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1039292003
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.826247283
Short name T19
Test name
Test status
Simulation time 92196953 ps
CPU time 1.89 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:53 PM PDT 24
Peak memory 204552 kb
Host smart-17b13f08-ab9d-47ee-b6f7-55cfbeb25f39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826247283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.826247283
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2587949650
Short name T21
Test name
Test status
Simulation time 129483680 ps
CPU time 2.02 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:57 PM PDT 24
Peak memory 204680 kb
Host smart-77365cfe-b67b-4a3f-b3bd-e8a12e78a4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587949650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2587949650
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3219124138
Short name T39
Test name
Test status
Simulation time 36913272 ps
CPU time 0.67 seconds
Started Aug 14 04:27:16 PM PDT 24
Finished Aug 14 04:27:16 PM PDT 24
Peak memory 204360 kb
Host smart-0bf7a52f-3cc3-4d65-9ab9-2adbd4d09b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219124138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3219124138
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1449072998
Short name T32
Test name
Test status
Simulation time 22026059 ps
CPU time 0.74 seconds
Started Aug 14 04:27:04 PM PDT 24
Finished Aug 14 04:27:05 PM PDT 24
Peak memory 204388 kb
Host smart-e26e2db6-f557-4fac-be1c-fe713bc9201b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449072998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1449072998
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2597575369
Short name T20
Test name
Test status
Simulation time 67178963 ps
CPU time 1.21 seconds
Started Aug 14 04:27:18 PM PDT 24
Finished Aug 14 04:27:19 PM PDT 24
Peak memory 204684 kb
Host smart-d0011fa5-3d64-4e17-aa61-0a45a41d784c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597575369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2597575369
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2877426605
Short name T50
Test name
Test status
Simulation time 114019757 ps
CPU time 0.66 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204352 kb
Host smart-48dbfaa2-2045-4d7d-92f9-3adfaa3b58a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877426605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2877426605
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.4276372591
Short name T80
Test name
Test status
Simulation time 21848346 ps
CPU time 0.63 seconds
Started Aug 14 04:26:46 PM PDT 24
Finished Aug 14 04:26:47 PM PDT 24
Peak memory 204312 kb
Host smart-cd402a0b-9140-4bc4-b22a-95378bf180b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276372591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4276372591
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1321510861
Short name T68
Test name
Test status
Simulation time 26185115 ps
CPU time 1.03 seconds
Started Aug 14 04:27:02 PM PDT 24
Finished Aug 14 04:27:03 PM PDT 24
Peak memory 204584 kb
Host smart-0946fa47-f605-4119-af9a-db2a73ceae4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321510861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1321510861
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2569256785
Short name T22
Test name
Test status
Simulation time 490650831 ps
CPU time 2.18 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204568 kb
Host smart-373848a4-db9f-465d-8b9f-29f291fd45a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569256785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2569256785
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2391243135
Short name T73
Test name
Test status
Simulation time 26644272 ps
CPU time 1.04 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204384 kb
Host smart-3f14d75f-1549-4754-a55e-94baa41bbed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391243135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2391243135
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.703029989
Short name T107
Test name
Test status
Simulation time 36140596 ps
CPU time 0.66 seconds
Started Aug 14 04:27:11 PM PDT 24
Finished Aug 14 04:27:12 PM PDT 24
Peak memory 204376 kb
Host smart-240e8d0a-683c-43e9-a41f-282fe49352c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703029989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.703029989
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.606878624
Short name T61
Test name
Test status
Simulation time 1349472956 ps
CPU time 2.08 seconds
Started Aug 14 04:27:06 PM PDT 24
Finished Aug 14 04:27:09 PM PDT 24
Peak memory 204664 kb
Host smart-1d20bd42-6728-4644-89cd-d79e7b993e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606878624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.606878624
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2011079847
Short name T140
Test name
Test status
Simulation time 67789541 ps
CPU time 0.66 seconds
Started Aug 14 04:27:14 PM PDT 24
Finished Aug 14 04:27:15 PM PDT 24
Peak memory 204364 kb
Host smart-5351d0b7-9b61-4e67-ab95-4caa3661c4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011079847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2011079847
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1046679881
Short name T59
Test name
Test status
Simulation time 571809444 ps
CPU time 2.08 seconds
Started Aug 14 04:27:02 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204640 kb
Host smart-658518ae-8607-4085-a910-dafd173bc7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046679881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1046679881
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.974627727
Short name T58
Test name
Test status
Simulation time 71815460 ps
CPU time 1.42 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204620 kb
Host smart-e00e24d0-e45a-4ea2-ae8e-90a2a0854f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974627727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.974627727
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3327823997
Short name T63
Test name
Test status
Simulation time 69694200 ps
CPU time 1.49 seconds
Started Aug 14 04:27:07 PM PDT 24
Finished Aug 14 04:27:09 PM PDT 24
Peak memory 204688 kb
Host smart-ed1c5db7-461d-4709-b1f4-da7a787b75ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327823997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3327823997
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1897871338
Short name T121
Test name
Test status
Simulation time 28749336 ps
CPU time 1.22 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204616 kb
Host smart-b5e27ffe-77b4-494b-867a-dc646016ca39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897871338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1897871338
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2385321548
Short name T27
Test name
Test status
Simulation time 209711043 ps
CPU time 2.63 seconds
Started Aug 14 04:27:01 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204532 kb
Host smart-5c563492-e1eb-4ac9-9a0b-d05731b09794
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385321548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2385321548
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.233896054
Short name T124
Test name
Test status
Simulation time 33065804 ps
CPU time 1.49 seconds
Started Aug 14 04:26:48 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 212964 kb
Host smart-3b3fc600-847d-40c6-9528-e6c5ed23dfcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233896054 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.233896054
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2597499349
Short name T133
Test name
Test status
Simulation time 178946723 ps
CPU time 0.78 seconds
Started Aug 14 04:26:48 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204448 kb
Host smart-5624e0ff-6865-4ac2-bda2-20b9e58d1cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597499349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2597499349
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1410287860
Short name T116
Test name
Test status
Simulation time 32397730 ps
CPU time 0.64 seconds
Started Aug 14 04:26:45 PM PDT 24
Finished Aug 14 04:26:46 PM PDT 24
Peak memory 204384 kb
Host smart-a831c1b2-bcf5-4d4f-be83-2f8243ee68ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410287860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1410287860
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2802699475
Short name T94
Test name
Test status
Simulation time 32496129 ps
CPU time 1.53 seconds
Started Aug 14 04:26:45 PM PDT 24
Finished Aug 14 04:26:46 PM PDT 24
Peak memory 204716 kb
Host smart-a15bd997-777d-4f56-a8a0-896037407df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802699475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2802699475
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.122510221
Short name T62
Test name
Test status
Simulation time 152771515 ps
CPU time 2.15 seconds
Started Aug 14 04:26:53 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 204584 kb
Host smart-8234aace-34cd-42ca-bf21-05cbf91d3adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122510221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.122510221
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1198807054
Short name T74
Test name
Test status
Simulation time 640108746 ps
CPU time 1.68 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204564 kb
Host smart-3487a34b-d585-4c9e-a805-77b29515fd49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198807054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1198807054
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1306998003
Short name T45
Test name
Test status
Simulation time 524841403 ps
CPU time 5.05 seconds
Started Aug 14 04:26:53 PM PDT 24
Finished Aug 14 04:26:59 PM PDT 24
Peak memory 204592 kb
Host smart-51cb7da4-3716-4cc1-b627-5b8b1ee47770
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306998003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1306998003
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2769888152
Short name T9
Test name
Test status
Simulation time 32888078 ps
CPU time 0.68 seconds
Started Aug 14 04:26:42 PM PDT 24
Finished Aug 14 04:26:43 PM PDT 24
Peak memory 204308 kb
Host smart-d4039a3d-6fd8-4991-9ee2-0d587b5839fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769888152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2769888152
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.193386008
Short name T101
Test name
Test status
Simulation time 117894989 ps
CPU time 0.93 seconds
Started Aug 14 04:26:41 PM PDT 24
Finished Aug 14 04:26:42 PM PDT 24
Peak memory 204472 kb
Host smart-41358bba-8531-48d2-9bfb-f588009b92dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193386008 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.193386008
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2966879428
Short name T153
Test name
Test status
Simulation time 36311535 ps
CPU time 0.69 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204396 kb
Host smart-394b3e44-fc06-4a44-b46d-600bb6b5e85e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966879428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2966879428
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3357134533
Short name T151
Test name
Test status
Simulation time 34712208 ps
CPU time 0.66 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:56 PM PDT 24
Peak memory 203596 kb
Host smart-43d60925-64c8-480b-bd02-0506eab0a8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357134533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3357134533
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.217125262
Short name T138
Test name
Test status
Simulation time 591235371 ps
CPU time 0.94 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204648 kb
Host smart-9f2cb2a1-c4c8-4478-9fbd-864ca6187f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217125262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.217125262
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3554879951
Short name T115
Test name
Test status
Simulation time 625307971 ps
CPU time 2.51 seconds
Started Aug 14 04:27:01 PM PDT 24
Finished Aug 14 04:27:03 PM PDT 24
Peak memory 204740 kb
Host smart-bd819556-a42d-4491-a573-f81912706238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554879951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3554879951
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2806689933
Short name T35
Test name
Test status
Simulation time 43004602 ps
CPU time 0.72 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204348 kb
Host smart-ddebbd06-5c5d-498a-bc2c-ab3f98cfe4d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806689933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2806689933
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4094563742
Short name T160
Test name
Test status
Simulation time 60175553 ps
CPU time 0.67 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:11 PM PDT 24
Peak memory 204348 kb
Host smart-4fcf1932-f423-4bf5-bc43-f22f704fd0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094563742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4094563742
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3039731684
Short name T47
Test name
Test status
Simulation time 115901436 ps
CPU time 0.88 seconds
Started Aug 14 04:27:11 PM PDT 24
Finished Aug 14 04:27:12 PM PDT 24
Peak memory 204476 kb
Host smart-b346b736-ddde-4f80-b04f-a71c9f94b05c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039731684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3039731684
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2808014340
Short name T13
Test name
Test status
Simulation time 30419800 ps
CPU time 1.49 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:56 PM PDT 24
Peak memory 204692 kb
Host smart-2d132dd7-6c2c-4afa-a047-8e21461d08eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808014340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2808014340
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.203675974
Short name T65
Test name
Test status
Simulation time 58925940 ps
CPU time 1.33 seconds
Started Aug 14 04:26:48 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204692 kb
Host smart-8ff5eff6-be81-4f86-a023-4846143984d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203675974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.203675974
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3535485563
Short name T119
Test name
Test status
Simulation time 78997162 ps
CPU time 0.81 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204484 kb
Host smart-e5031866-f20b-4a8b-af0b-01740e873697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535485563 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3535485563
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3117176897
Short name T136
Test name
Test status
Simulation time 24607623 ps
CPU time 0.77 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:53 PM PDT 24
Peak memory 204380 kb
Host smart-39cc1dbc-94ab-4b7c-9ae4-1dc4ad3087f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117176897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3117176897
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.457049752
Short name T26
Test name
Test status
Simulation time 170355147 ps
CPU time 1.14 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204640 kb
Host smart-fbb5a76d-777b-407c-b6af-6d8de2787c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457049752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.457049752
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3941535960
Short name T142
Test name
Test status
Simulation time 475951775 ps
CPU time 2.07 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:12 PM PDT 24
Peak memory 204688 kb
Host smart-5ad5ff6e-2e50-4b88-b93a-1976660f0b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941535960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3941535960
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1523755146
Short name T87
Test name
Test status
Simulation time 172128721 ps
CPU time 1.18 seconds
Started Aug 14 04:26:53 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 212924 kb
Host smart-43c9a748-cde9-46af-894f-577c8004d8dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523755146 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1523755146
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794134392
Short name T84
Test name
Test status
Simulation time 76940787 ps
CPU time 0.74 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204340 kb
Host smart-238122d6-315d-4710-92ab-f7cf009a1f0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794134392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2794134392
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3021185884
Short name T123
Test name
Test status
Simulation time 41209643 ps
CPU time 0.64 seconds
Started Aug 14 04:26:54 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204348 kb
Host smart-0bb26761-e962-4efd-9973-97a2f983335e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021185884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3021185884
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2244265555
Short name T159
Test name
Test status
Simulation time 57477961 ps
CPU time 1.2 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204496 kb
Host smart-fc69f701-5c42-4166-8202-d6484c1d5465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244265555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2244265555
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1479294449
Short name T127
Test name
Test status
Simulation time 152375093 ps
CPU time 2.09 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204708 kb
Host smart-d0849ed6-c323-4752-bfe7-627bc8502f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479294449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1479294449
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4186435787
Short name T64
Test name
Test status
Simulation time 61226354 ps
CPU time 1.29 seconds
Started Aug 14 04:26:54 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 204608 kb
Host smart-75b6e745-b91e-45ea-a5bb-ec38f80a03ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186435787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4186435787
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3535122939
Short name T141
Test name
Test status
Simulation time 34065900 ps
CPU time 1.5 seconds
Started Aug 14 04:27:00 PM PDT 24
Finished Aug 14 04:27:02 PM PDT 24
Peak memory 212904 kb
Host smart-1bdb99f5-3e8b-4714-b48a-cfc7d47d3239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535122939 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3535122939
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2723461550
Short name T34
Test name
Test status
Simulation time 28355324 ps
CPU time 0.78 seconds
Started Aug 14 04:27:06 PM PDT 24
Finished Aug 14 04:27:07 PM PDT 24
Peak memory 204324 kb
Host smart-7f01ddec-6846-43cf-9472-0608bd3204cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723461550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2723461550
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2517944183
Short name T48
Test name
Test status
Simulation time 45555223 ps
CPU time 0.61 seconds
Started Aug 14 04:27:00 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204280 kb
Host smart-5dc50eb1-568d-4807-af76-168feff1694e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517944183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2517944183
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.121390751
Short name T75
Test name
Test status
Simulation time 117139078 ps
CPU time 1.05 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204616 kb
Host smart-546681e3-b089-410a-a89d-7c41e9027041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121390751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.121390751
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3529366689
Short name T15
Test name
Test status
Simulation time 39149951 ps
CPU time 1.92 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204692 kb
Host smart-f6027943-44e1-4ebb-8a70-c8da40b1ab5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529366689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3529366689
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1689318572
Short name T51
Test name
Test status
Simulation time 81992125 ps
CPU time 1.41 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204712 kb
Host smart-43db5ccd-c785-4e36-8a6c-580b1018f04b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689318572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1689318572
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1637524985
Short name T102
Test name
Test status
Simulation time 264956401 ps
CPU time 0.82 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204528 kb
Host smart-703c2ece-de4d-4a26-912d-c63e274f5e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637524985 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1637524985
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2419688277
Short name T41
Test name
Test status
Simulation time 83339124 ps
CPU time 0.84 seconds
Started Aug 14 04:26:54 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 204376 kb
Host smart-dcb9d39a-67b3-47d9-b9d7-d924fa52bf57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419688277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2419688277
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3002163099
Short name T38
Test name
Test status
Simulation time 20886201 ps
CPU time 0.67 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 204360 kb
Host smart-efa64db0-df36-475e-9ae3-53f1a2fa9e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002163099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3002163099
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3912277942
Short name T85
Test name
Test status
Simulation time 22559553 ps
CPU time 0.88 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:53 PM PDT 24
Peak memory 204448 kb
Host smart-79907749-e830-4f6b-8303-707b497bf950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912277942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3912277942
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1685912915
Short name T66
Test name
Test status
Simulation time 277600396 ps
CPU time 1.4 seconds
Started Aug 14 04:27:06 PM PDT 24
Finished Aug 14 04:27:07 PM PDT 24
Peak memory 204552 kb
Host smart-1ca4f047-a1a5-49dc-ae58-50b0b738ef39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685912915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1685912915
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.705459689
Short name T4
Test name
Test status
Simulation time 189874287 ps
CPU time 0.72 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204496 kb
Host smart-16593357-6332-47d3-8c6d-12dc3d32616d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705459689 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.705459689
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3798717082
Short name T93
Test name
Test status
Simulation time 31888519 ps
CPU time 0.66 seconds
Started Aug 14 04:27:01 PM PDT 24
Finished Aug 14 04:27:02 PM PDT 24
Peak memory 204372 kb
Host smart-c36f8783-a731-4318-a945-3511fbc3584d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798717082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3798717082
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2630589555
Short name T23
Test name
Test status
Simulation time 203780335 ps
CPU time 1.13 seconds
Started Aug 14 04:27:15 PM PDT 24
Finished Aug 14 04:27:16 PM PDT 24
Peak memory 204644 kb
Host smart-e95d0ca8-bd5b-4902-8aec-7b0b22a96892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630589555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2630589555
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3347920883
Short name T145
Test name
Test status
Simulation time 109854176 ps
CPU time 2.34 seconds
Started Aug 14 04:27:19 PM PDT 24
Finished Aug 14 04:27:21 PM PDT 24
Peak memory 204708 kb
Host smart-a3ec8b87-a2bc-455e-9265-0646fc28af75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347920883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3347920883
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2160741349
Short name T53
Test name
Test status
Simulation time 396076760 ps
CPU time 1 seconds
Started Aug 14 04:27:04 PM PDT 24
Finished Aug 14 04:27:05 PM PDT 24
Peak memory 204484 kb
Host smart-4a06432f-d223-40ec-9b62-4c7a811d66e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160741349 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2160741349
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2513209311
Short name T25
Test name
Test status
Simulation time 68738503 ps
CPU time 0.87 seconds
Started Aug 14 04:27:15 PM PDT 24
Finished Aug 14 04:27:16 PM PDT 24
Peak memory 204300 kb
Host smart-8655cd07-1a9d-4a11-8ff8-8e85463b6db2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513209311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2513209311
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3538962507
Short name T82
Test name
Test status
Simulation time 16485915 ps
CPU time 0.65 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:10 PM PDT 24
Peak memory 204364 kb
Host smart-80ebf8ad-3475-4cb1-9631-c2a009e5798e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538962507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3538962507
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3939528871
Short name T70
Test name
Test status
Simulation time 124687446 ps
CPU time 1.2 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204688 kb
Host smart-8390632f-a0c6-4c95-a7fa-5379965fcb4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939528871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3939528871
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3858989795
Short name T118
Test name
Test status
Simulation time 86739306 ps
CPU time 2.35 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:53 PM PDT 24
Peak memory 212896 kb
Host smart-5282237f-8681-4f0d-a775-2ecee52ff461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858989795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3858989795
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1173510766
Short name T126
Test name
Test status
Simulation time 70662010 ps
CPU time 0.96 seconds
Started Aug 14 04:27:08 PM PDT 24
Finished Aug 14 04:27:09 PM PDT 24
Peak memory 204476 kb
Host smart-d02f8173-f0ec-4e8c-bbd9-899d4610121d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173510766 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1173510766
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3145901722
Short name T117
Test name
Test status
Simulation time 55037076 ps
CPU time 0.73 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:11 PM PDT 24
Peak memory 204380 kb
Host smart-d6c62fa8-503c-420a-b340-1de0e8eeac34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145901722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3145901722
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2787427635
Short name T100
Test name
Test status
Simulation time 76555027 ps
CPU time 1.03 seconds
Started Aug 14 04:26:56 PM PDT 24
Finished Aug 14 04:26:57 PM PDT 24
Peak memory 204352 kb
Host smart-c8a9484c-037f-4511-8307-925655887d02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787427635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2787427635
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.781189845
Short name T54
Test name
Test status
Simulation time 220349475 ps
CPU time 1.62 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204708 kb
Host smart-8e3c9441-f0ad-43ea-8d2b-4deff01c33fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781189845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.781189845
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.767901275
Short name T114
Test name
Test status
Simulation time 189930482 ps
CPU time 0.79 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:53 PM PDT 24
Peak memory 204528 kb
Host smart-57e2b695-2d8a-4a1c-8f79-330fe05471fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767901275 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.767901275
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3553206869
Short name T46
Test name
Test status
Simulation time 21362450 ps
CPU time 0.66 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:10 PM PDT 24
Peak memory 204372 kb
Host smart-ea321740-4503-4e75-9de3-3f6ec5546733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553206869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3553206869
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1655454878
Short name T49
Test name
Test status
Simulation time 43652021 ps
CPU time 0.66 seconds
Started Aug 14 04:27:00 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204316 kb
Host smart-a1bad375-4f25-4223-b987-7c9c9bff9230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655454878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1655454878
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.812489652
Short name T10
Test name
Test status
Simulation time 281797912 ps
CPU time 1.13 seconds
Started Aug 14 04:27:01 PM PDT 24
Finished Aug 14 04:27:02 PM PDT 24
Peak memory 204592 kb
Host smart-0fa4f130-8755-41d9-a271-c85abfb3777e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812489652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.812489652
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2567857558
Short name T132
Test name
Test status
Simulation time 92600240 ps
CPU time 2.48 seconds
Started Aug 14 04:27:08 PM PDT 24
Finished Aug 14 04:27:11 PM PDT 24
Peak memory 212844 kb
Host smart-ea17f6e5-6221-45b4-af89-4c9ea0d7c676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567857558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2567857558
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.292944750
Short name T56
Test name
Test status
Simulation time 47142845 ps
CPU time 1.36 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:57 PM PDT 24
Peak memory 203732 kb
Host smart-b9a2890c-b790-44df-b07f-0e17402a78a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292944750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.292944750
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2460657318
Short name T2
Test name
Test status
Simulation time 65052382 ps
CPU time 0.75 seconds
Started Aug 14 04:27:12 PM PDT 24
Finished Aug 14 04:27:13 PM PDT 24
Peak memory 204500 kb
Host smart-888fe149-0722-4106-8f70-3e2e48ccfa90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460657318 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2460657318
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1701649460
Short name T44
Test name
Test status
Simulation time 29421529 ps
CPU time 0.79 seconds
Started Aug 14 04:27:17 PM PDT 24
Finished Aug 14 04:27:18 PM PDT 24
Peak memory 204380 kb
Host smart-9c93cba2-cf82-4851-a874-20bcc3bc5c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701649460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1701649460
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3417813545
Short name T148
Test name
Test status
Simulation time 156450201 ps
CPU time 0.65 seconds
Started Aug 14 04:27:19 PM PDT 24
Finished Aug 14 04:27:19 PM PDT 24
Peak memory 204364 kb
Host smart-53e3c7d0-ee4c-4bc9-977e-a32458e9be39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417813545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3417813545
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.908737528
Short name T71
Test name
Test status
Simulation time 73368262 ps
CPU time 1.09 seconds
Started Aug 14 04:26:58 PM PDT 24
Finished Aug 14 04:26:59 PM PDT 24
Peak memory 204572 kb
Host smart-2571eb4e-cb49-45e2-9089-a48c05ebf0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908737528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.908737528
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1803498831
Short name T86
Test name
Test status
Simulation time 89274886 ps
CPU time 1.41 seconds
Started Aug 14 04:26:57 PM PDT 24
Finished Aug 14 04:26:58 PM PDT 24
Peak memory 204652 kb
Host smart-0b559967-fcae-4b0d-9fad-b8b32767d6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803498831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1803498831
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1017393095
Short name T67
Test name
Test status
Simulation time 282289654 ps
CPU time 2.03 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204636 kb
Host smart-d8122ac4-6a84-40f8-9916-f9256ab3b781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017393095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1017393095
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.633783636
Short name T29
Test name
Test status
Simulation time 56486694 ps
CPU time 1.2 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204548 kb
Host smart-1eeb518f-9844-44eb-95e6-13db6a999be4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633783636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.633783636
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.73138018
Short name T96
Test name
Test status
Simulation time 722413200 ps
CPU time 2.7 seconds
Started Aug 14 04:26:47 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204372 kb
Host smart-dbcc8f88-04b3-46c7-95a6-fdf2b1c5a6d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73138018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.73138018
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2613617784
Short name T33
Test name
Test status
Simulation time 30612453 ps
CPU time 0.76 seconds
Started Aug 14 04:26:59 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204392 kb
Host smart-3193770c-fcbf-429a-bc4e-a3cabba5172c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613617784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2613617784
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3137544528
Short name T143
Test name
Test status
Simulation time 44274307 ps
CPU time 0.8 seconds
Started Aug 14 04:26:46 PM PDT 24
Finished Aug 14 04:26:47 PM PDT 24
Peak memory 204532 kb
Host smart-dffc876c-a902-48c4-93a4-d2b3d5dd19c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137544528 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3137544528
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1019705569
Short name T8
Test name
Test status
Simulation time 24175304 ps
CPU time 0.67 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204388 kb
Host smart-0b445a66-5a7b-4ff2-966d-a38662e79dea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019705569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1019705569
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2199939428
Short name T81
Test name
Test status
Simulation time 29630139 ps
CPU time 0.66 seconds
Started Aug 14 04:26:58 PM PDT 24
Finished Aug 14 04:26:59 PM PDT 24
Peak memory 204380 kb
Host smart-ad867a42-a1fd-4844-873e-1e98ac26b919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199939428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2199939428
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3327141324
Short name T72
Test name
Test status
Simulation time 34728740 ps
CPU time 0.91 seconds
Started Aug 14 04:26:39 PM PDT 24
Finished Aug 14 04:26:40 PM PDT 24
Peak memory 204420 kb
Host smart-c6fc801a-6a5d-4e9a-ba35-4f0750de15db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327141324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3327141324
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2936132064
Short name T125
Test name
Test status
Simulation time 74509683 ps
CPU time 1.3 seconds
Started Aug 14 04:26:42 PM PDT 24
Finished Aug 14 04:26:43 PM PDT 24
Peak memory 204720 kb
Host smart-04c3b77d-4020-4e1f-a2d5-e41480d1b8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936132064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2936132064
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2296800190
Short name T55
Test name
Test status
Simulation time 127592523 ps
CPU time 1.41 seconds
Started Aug 14 04:26:46 PM PDT 24
Finished Aug 14 04:26:47 PM PDT 24
Peak memory 204684 kb
Host smart-b0c7249c-1e8e-4dcf-a47f-89d092d37096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296800190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2296800190
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3265285376
Short name T111
Test name
Test status
Simulation time 43024722 ps
CPU time 0.63 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:03 PM PDT 24
Peak memory 204356 kb
Host smart-b3a2e22b-f2a8-416a-b2b9-23b3c1f815a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265285376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3265285376
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4107971361
Short name T106
Test name
Test status
Simulation time 21484399 ps
CPU time 0.65 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:10 PM PDT 24
Peak memory 204376 kb
Host smart-f9ec0bad-2767-4267-9654-4fa7c9bce7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107971361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4107971361
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.5431703
Short name T150
Test name
Test status
Simulation time 19665745 ps
CPU time 0.62 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204348 kb
Host smart-74b98f80-15a4-4a28-b36e-9822e2922104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5431703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.5431703
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2982753139
Short name T79
Test name
Test status
Simulation time 28225326 ps
CPU time 0.74 seconds
Started Aug 14 04:27:17 PM PDT 24
Finished Aug 14 04:27:18 PM PDT 24
Peak memory 204352 kb
Host smart-ea75dda4-a82b-4215-88df-14de160d38ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982753139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2982753139
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1644172321
Short name T98
Test name
Test status
Simulation time 27738544 ps
CPU time 0.67 seconds
Started Aug 14 04:27:19 PM PDT 24
Finished Aug 14 04:27:20 PM PDT 24
Peak memory 204368 kb
Host smart-c6d4f033-cfb4-4310-8b04-dbe46c8feb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644172321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1644172321
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3236680084
Short name T42
Test name
Test status
Simulation time 20358360 ps
CPU time 0.66 seconds
Started Aug 14 04:27:00 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204360 kb
Host smart-dee9a3ac-0248-47ca-9f10-b5aa8284e05d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236680084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3236680084
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.224511346
Short name T137
Test name
Test status
Simulation time 16551716 ps
CPU time 0.64 seconds
Started Aug 14 04:27:11 PM PDT 24
Finished Aug 14 04:27:11 PM PDT 24
Peak memory 204360 kb
Host smart-018cde94-5478-474c-ada0-f275875fa86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224511346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.224511346
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.350212811
Short name T89
Test name
Test status
Simulation time 33448034 ps
CPU time 0.67 seconds
Started Aug 14 04:27:16 PM PDT 24
Finished Aug 14 04:27:17 PM PDT 24
Peak memory 204340 kb
Host smart-df3e6e20-8145-4316-8480-b5a44c1c2a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350212811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.350212811
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.899505154
Short name T83
Test name
Test status
Simulation time 15753168 ps
CPU time 0.67 seconds
Started Aug 14 04:27:08 PM PDT 24
Finished Aug 14 04:27:08 PM PDT 24
Peak memory 204388 kb
Host smart-f14575af-a7f6-4d79-9c80-580bb5c44f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899505154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.899505154
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.70207310
Short name T165
Test name
Test status
Simulation time 19010785 ps
CPU time 0.67 seconds
Started Aug 14 04:27:18 PM PDT 24
Finished Aug 14 04:27:19 PM PDT 24
Peak memory 204376 kb
Host smart-6a7ad7bd-905e-4549-b085-5c81137b680d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70207310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.70207310
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2704806973
Short name T43
Test name
Test status
Simulation time 125123466 ps
CPU time 1.23 seconds
Started Aug 14 04:26:53 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204564 kb
Host smart-1750de07-d8e8-4e4b-b876-911ae06b7694
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704806973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2704806973
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1399816404
Short name T97
Test name
Test status
Simulation time 2507396915 ps
CPU time 2.59 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204652 kb
Host smart-d4dbd72e-9a84-4db6-993d-71ffc0ea9de7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399816404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1399816404
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1807740327
Short name T36
Test name
Test status
Simulation time 88820019 ps
CPU time 0.79 seconds
Started Aug 14 04:26:53 PM PDT 24
Finished Aug 14 04:26:59 PM PDT 24
Peak memory 204348 kb
Host smart-3e771089-5880-4b22-bd26-a16ec21c62f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807740327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1807740327
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3558113285
Short name T18
Test name
Test status
Simulation time 34702608 ps
CPU time 0.92 seconds
Started Aug 14 04:26:43 PM PDT 24
Finished Aug 14 04:26:44 PM PDT 24
Peak memory 204468 kb
Host smart-4a8f0641-4b1b-4390-9b05-36024ad2edb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558113285 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3558113285
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.163852174
Short name T164
Test name
Test status
Simulation time 22539329 ps
CPU time 0.72 seconds
Started Aug 14 04:26:48 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204348 kb
Host smart-56c27035-fade-4ee9-8501-dd6bdd27ffce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163852174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.163852174
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.996226102
Short name T155
Test name
Test status
Simulation time 50202876 ps
CPU time 0.79 seconds
Started Aug 14 04:27:02 PM PDT 24
Finished Aug 14 04:27:03 PM PDT 24
Peak memory 204448 kb
Host smart-dadb3be4-ffa7-45c8-a926-779dcdec22aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996226102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.996226102
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.432975189
Short name T17
Test name
Test status
Simulation time 261095666 ps
CPU time 2.21 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204764 kb
Host smart-04635b4c-39d9-4738-8d64-bf7e37d74ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432975189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.432975189
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1634872182
Short name T109
Test name
Test status
Simulation time 14629967 ps
CPU time 0.7 seconds
Started Aug 14 04:27:20 PM PDT 24
Finished Aug 14 04:27:21 PM PDT 24
Peak memory 204356 kb
Host smart-0b2ba5f2-1583-44c3-8ff2-77297552e080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634872182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1634872182
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2571171314
Short name T144
Test name
Test status
Simulation time 19221743 ps
CPU time 0.68 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 204348 kb
Host smart-f051ca7b-1540-4b30-87e3-92b8351f50c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571171314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2571171314
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3060741437
Short name T120
Test name
Test status
Simulation time 38171408 ps
CPU time 0.67 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 204348 kb
Host smart-766c8ffe-ba4a-46ac-8aeb-53f0f66c2423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060741437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3060741437
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1897504577
Short name T11
Test name
Test status
Simulation time 42462232 ps
CPU time 0.67 seconds
Started Aug 14 04:27:07 PM PDT 24
Finished Aug 14 04:27:07 PM PDT 24
Peak memory 204364 kb
Host smart-0bf2d37d-2e9f-41f6-8d8b-4b8b3f946684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897504577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1897504577
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2141680144
Short name T108
Test name
Test status
Simulation time 48605220 ps
CPU time 0.62 seconds
Started Aug 14 04:27:13 PM PDT 24
Finished Aug 14 04:27:13 PM PDT 24
Peak memory 204364 kb
Host smart-d47ded58-36d3-47e4-87c2-c3df2aec78f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141680144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2141680144
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2929277578
Short name T40
Test name
Test status
Simulation time 20489826 ps
CPU time 0.67 seconds
Started Aug 14 04:27:17 PM PDT 24
Finished Aug 14 04:27:18 PM PDT 24
Peak memory 204416 kb
Host smart-d3b8a78d-75cc-4e2b-804a-6bc9d4b3a8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929277578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2929277578
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1659698518
Short name T161
Test name
Test status
Simulation time 19239312 ps
CPU time 0.66 seconds
Started Aug 14 04:27:27 PM PDT 24
Finished Aug 14 04:27:28 PM PDT 24
Peak memory 204408 kb
Host smart-620cefff-3309-4753-a03e-c62013def365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659698518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1659698518
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2316323003
Short name T130
Test name
Test status
Simulation time 111042174 ps
CPU time 0.65 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 204360 kb
Host smart-6c522c95-3bc4-4a37-bfea-94312875162c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316323003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2316323003
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3560059032
Short name T91
Test name
Test status
Simulation time 49001815 ps
CPU time 0.63 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:22 PM PDT 24
Peak memory 204344 kb
Host smart-1caaeb76-f0d3-432a-8095-c0dc1060cf01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560059032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3560059032
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2884707623
Short name T31
Test name
Test status
Simulation time 114017526 ps
CPU time 4.46 seconds
Started Aug 14 04:26:57 PM PDT 24
Finished Aug 14 04:27:01 PM PDT 24
Peak memory 204552 kb
Host smart-bfadb382-1f88-482d-a481-7002b65f6f22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884707623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2884707623
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3143287006
Short name T76
Test name
Test status
Simulation time 28846944 ps
CPU time 0.67 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204348 kb
Host smart-c60a648c-ba3b-4a65-85b8-7f773859e993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143287006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3143287006
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.993462109
Short name T128
Test name
Test status
Simulation time 29535044 ps
CPU time 1.23 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204752 kb
Host smart-3f99aafa-e5cc-42fb-b57e-19b607111d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993462109 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.993462109
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2249374213
Short name T7
Test name
Test status
Simulation time 24381471 ps
CPU time 0.78 seconds
Started Aug 14 04:26:45 PM PDT 24
Finished Aug 14 04:26:46 PM PDT 24
Peak memory 204376 kb
Host smart-778422a4-77d9-4880-a6a7-9bcecd24993a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249374213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2249374213
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1727602324
Short name T158
Test name
Test status
Simulation time 28152499 ps
CPU time 0.64 seconds
Started Aug 14 04:26:54 PM PDT 24
Finished Aug 14 04:26:55 PM PDT 24
Peak memory 204380 kb
Host smart-6e5f7f41-6c39-4266-99d5-3ce58fc44518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727602324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1727602324
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3651184136
Short name T90
Test name
Test status
Simulation time 30340843 ps
CPU time 1.35 seconds
Started Aug 14 04:26:52 PM PDT 24
Finished Aug 14 04:26:54 PM PDT 24
Peak memory 204700 kb
Host smart-74d83394-dea8-466a-8ffa-4a38a5bdfa50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651184136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3651184136
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.199352301
Short name T60
Test name
Test status
Simulation time 78468134 ps
CPU time 1.37 seconds
Started Aug 14 04:26:56 PM PDT 24
Finished Aug 14 04:27:02 PM PDT 24
Peak memory 204672 kb
Host smart-735b19aa-dcad-4cee-867a-bad9476f5683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199352301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.199352301
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3855960011
Short name T95
Test name
Test status
Simulation time 26624948 ps
CPU time 0.7 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 204368 kb
Host smart-4ce8e42f-a799-4ccf-957f-e7b5975256bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855960011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3855960011
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.495148493
Short name T113
Test name
Test status
Simulation time 265695664 ps
CPU time 0.65 seconds
Started Aug 14 04:27:15 PM PDT 24
Finished Aug 14 04:27:16 PM PDT 24
Peak memory 204352 kb
Host smart-96f56ca0-252f-464e-a9d8-9fb8b81b70be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495148493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.495148493
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2828540473
Short name T135
Test name
Test status
Simulation time 18374323 ps
CPU time 0.66 seconds
Started Aug 14 04:27:19 PM PDT 24
Finished Aug 14 04:27:20 PM PDT 24
Peak memory 204356 kb
Host smart-c8822f61-9615-4116-86f0-37339a5f4100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828540473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2828540473
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.555313037
Short name T88
Test name
Test status
Simulation time 30615532 ps
CPU time 0.69 seconds
Started Aug 14 04:27:17 PM PDT 24
Finished Aug 14 04:27:18 PM PDT 24
Peak memory 204380 kb
Host smart-aa8688e7-ca24-489b-8005-3d4e3a0b0ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555313037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.555313037
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.612063642
Short name T147
Test name
Test status
Simulation time 23771871 ps
CPU time 0.69 seconds
Started Aug 14 04:27:15 PM PDT 24
Finished Aug 14 04:27:15 PM PDT 24
Peak memory 204356 kb
Host smart-a9fea407-54f9-43bd-a087-ba3af974d735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612063642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.612063642
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.4129934412
Short name T77
Test name
Test status
Simulation time 50154034 ps
CPU time 0.65 seconds
Started Aug 14 04:27:04 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204316 kb
Host smart-6e9e2363-964d-4e79-87d8-f66365628078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129934412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.4129934412
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1172587601
Short name T129
Test name
Test status
Simulation time 17297003 ps
CPU time 0.77 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 204352 kb
Host smart-1a921042-e282-4664-8476-7c5813ca4b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172587601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1172587601
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1487763775
Short name T122
Test name
Test status
Simulation time 17988366 ps
CPU time 0.7 seconds
Started Aug 14 04:27:07 PM PDT 24
Finished Aug 14 04:27:08 PM PDT 24
Peak memory 204364 kb
Host smart-be76f801-db65-4f06-8d1a-859481d95efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487763775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1487763775
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2977233946
Short name T78
Test name
Test status
Simulation time 19385091 ps
CPU time 0.67 seconds
Started Aug 14 04:27:20 PM PDT 24
Finished Aug 14 04:27:21 PM PDT 24
Peak memory 204360 kb
Host smart-f45a524f-4a70-4966-ab24-ac2605bb087c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977233946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2977233946
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3263491374
Short name T110
Test name
Test status
Simulation time 136001070 ps
CPU time 0.92 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204512 kb
Host smart-4f9f4055-aa45-4a83-b79b-7759b9aa4508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263491374 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3263491374
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.987582645
Short name T28
Test name
Test status
Simulation time 95769064 ps
CPU time 0.77 seconds
Started Aug 14 04:26:57 PM PDT 24
Finished Aug 14 04:26:58 PM PDT 24
Peak memory 204380 kb
Host smart-5f4389c8-484a-4445-855b-59b13bc23d9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987582645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.987582645
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3703291554
Short name T163
Test name
Test status
Simulation time 18114746 ps
CPU time 0.69 seconds
Started Aug 14 04:26:42 PM PDT 24
Finished Aug 14 04:26:43 PM PDT 24
Peak memory 204356 kb
Host smart-2ee522e4-e178-4565-b0c8-c2ef9c0a1e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703291554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3703291554
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3667627192
Short name T24
Test name
Test status
Simulation time 39622951 ps
CPU time 0.89 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204448 kb
Host smart-76f284ad-8138-4921-a3c9-46b2addb09cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667627192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3667627192
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1068092724
Short name T154
Test name
Test status
Simulation time 206752286 ps
CPU time 2.09 seconds
Started Aug 14 04:26:47 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204700 kb
Host smart-197f0fff-5743-4bcd-b151-45dd69044dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068092724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1068092724
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1195734935
Short name T152
Test name
Test status
Simulation time 153761811 ps
CPU time 2.25 seconds
Started Aug 14 04:26:47 PM PDT 24
Finished Aug 14 04:26:49 PM PDT 24
Peak memory 204660 kb
Host smart-64bee967-d49d-492a-875a-3db0169f5cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195734935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1195734935
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2363242210
Short name T112
Test name
Test status
Simulation time 20636382 ps
CPU time 0.92 seconds
Started Aug 14 04:26:51 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 204524 kb
Host smart-c4391e49-5a35-4ae1-aadd-9d66f71f4aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363242210 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2363242210
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.863831085
Short name T30
Test name
Test status
Simulation time 17953147 ps
CPU time 0.69 seconds
Started Aug 14 04:26:55 PM PDT 24
Finished Aug 14 04:26:56 PM PDT 24
Peak memory 204292 kb
Host smart-448b5389-4483-40a3-87f9-ad983407d97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863831085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.863831085
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2400538094
Short name T12
Test name
Test status
Simulation time 17672974 ps
CPU time 0.67 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204336 kb
Host smart-bd339d48-af1b-4984-b3f1-a2db01912541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400538094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2400538094
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2718817516
Short name T69
Test name
Test status
Simulation time 22795161 ps
CPU time 0.89 seconds
Started Aug 14 04:27:06 PM PDT 24
Finished Aug 14 04:27:07 PM PDT 24
Peak memory 204416 kb
Host smart-74bbd3e1-a87c-4975-b62f-4cdbcef61fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718817516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2718817516
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3716641566
Short name T105
Test name
Test status
Simulation time 124169618 ps
CPU time 1.85 seconds
Started Aug 14 04:26:57 PM PDT 24
Finished Aug 14 04:26:59 PM PDT 24
Peak memory 204732 kb
Host smart-f02996a3-3686-4a91-8e3f-85f0e58fb7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716641566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3716641566
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2085497405
Short name T57
Test name
Test status
Simulation time 273249782 ps
CPU time 2.07 seconds
Started Aug 14 04:27:01 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204560 kb
Host smart-82041018-9d3d-4a58-b5bb-b9ecd78b7934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085497405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2085497405
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4233865002
Short name T103
Test name
Test status
Simulation time 81903322 ps
CPU time 0.8 seconds
Started Aug 14 04:26:46 PM PDT 24
Finished Aug 14 04:26:47 PM PDT 24
Peak memory 204528 kb
Host smart-5c795592-6a6e-4289-96eb-4cb485b321d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233865002 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4233865002
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2543770971
Short name T157
Test name
Test status
Simulation time 74466715 ps
CPU time 0.79 seconds
Started Aug 14 04:27:30 PM PDT 24
Finished Aug 14 04:27:31 PM PDT 24
Peak memory 204384 kb
Host smart-bffaa137-59d0-4947-bc03-97151167dbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543770971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2543770971
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.39548824
Short name T37
Test name
Test status
Simulation time 42473995 ps
CPU time 0.69 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204328 kb
Host smart-cbbd7748-121e-4849-b4e2-1c70f7e925a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.39548824
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1391191408
Short name T162
Test name
Test status
Simulation time 31482434 ps
CPU time 1.08 seconds
Started Aug 14 04:26:48 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204628 kb
Host smart-8cfeca30-7714-4744-8430-c69a9d21d2b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391191408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1391191408
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.967496053
Short name T52
Test name
Test status
Simulation time 618829972 ps
CPU time 2.63 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:52 PM PDT 24
Peak memory 212840 kb
Host smart-904448aa-ce2a-48d3-9909-22322b9db275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967496053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.967496053
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1013613180
Short name T16
Test name
Test status
Simulation time 150168520 ps
CPU time 1.34 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204588 kb
Host smart-03412e81-d040-4f97-9fca-302df3ec1eff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013613180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1013613180
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1298702007
Short name T92
Test name
Test status
Simulation time 84403911 ps
CPU time 1.1 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 204776 kb
Host smart-ae6319d9-8fe7-4729-a833-e4698af4ad76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298702007 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1298702007
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1459965340
Short name T149
Test name
Test status
Simulation time 188873218 ps
CPU time 0.67 seconds
Started Aug 14 04:27:11 PM PDT 24
Finished Aug 14 04:27:12 PM PDT 24
Peak memory 204324 kb
Host smart-4e61ffe2-5f25-45b7-84e1-f95d99da70a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459965340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1459965340
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3745755791
Short name T139
Test name
Test status
Simulation time 75279780 ps
CPU time 0.67 seconds
Started Aug 14 04:27:03 PM PDT 24
Finished Aug 14 04:27:04 PM PDT 24
Peak memory 204376 kb
Host smart-9a89612a-afab-4a7f-9376-8856b242eaf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745755791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3745755791
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.473079384
Short name T6
Test name
Test status
Simulation time 58540628 ps
CPU time 1.38 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204680 kb
Host smart-778dde55-4588-4327-a66c-f619196c3f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473079384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.473079384
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.748390978
Short name T131
Test name
Test status
Simulation time 301156671 ps
CPU time 1.35 seconds
Started Aug 14 04:26:49 PM PDT 24
Finished Aug 14 04:26:50 PM PDT 24
Peak memory 204636 kb
Host smart-cd58b2a3-17a3-44c7-bf5a-7d0814735070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748390978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.748390978
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1687403891
Short name T146
Test name
Test status
Simulation time 116525901 ps
CPU time 0.82 seconds
Started Aug 14 04:26:50 PM PDT 24
Finished Aug 14 04:26:51 PM PDT 24
Peak memory 204488 kb
Host smart-e55f3a63-376e-4082-85a5-a854f002bfd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687403891 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1687403891
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1171845298
Short name T99
Test name
Test status
Simulation time 44844702 ps
CPU time 0.75 seconds
Started Aug 14 04:27:13 PM PDT 24
Finished Aug 14 04:27:13 PM PDT 24
Peak memory 204340 kb
Host smart-7d6507c3-7d40-41a7-884b-664dce79ea3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171845298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1171845298
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2169857675
Short name T3
Test name
Test status
Simulation time 48071450 ps
CPU time 0.71 seconds
Started Aug 14 04:27:20 PM PDT 24
Finished Aug 14 04:27:21 PM PDT 24
Peak memory 204360 kb
Host smart-a55a41b5-c5df-4e5c-adc6-a31c9a082dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169857675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2169857675
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1325566037
Short name T104
Test name
Test status
Simulation time 110266132 ps
CPU time 1.19 seconds
Started Aug 14 04:27:10 PM PDT 24
Finished Aug 14 04:27:12 PM PDT 24
Peak memory 204616 kb
Host smart-39a537c5-ea62-4d7b-8e92-3f8899a168e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325566037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1325566037
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1152045870
Short name T134
Test name
Test status
Simulation time 55953407 ps
CPU time 1.33 seconds
Started Aug 14 04:26:58 PM PDT 24
Finished Aug 14 04:27:00 PM PDT 24
Peak memory 204744 kb
Host smart-d6b50dfa-7a14-44cb-b8d7-5041abf29019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152045870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1152045870
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2037750356
Short name T156
Test name
Test status
Simulation time 54632495 ps
CPU time 1.35 seconds
Started Aug 14 04:27:05 PM PDT 24
Finished Aug 14 04:27:06 PM PDT 24
Peak memory 204664 kb
Host smart-402b6817-303c-4b3b-89d5-8786b54d1612
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037750356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2037750356
Directory /workspace/9.i2c_tl_intg_err/latest
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