Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	339	1			T1	8		T3	8		T6	1
all_pins[1]	339	1			T1	8		T3	8		T6	1
all_pins[2]	339	1			T1	8		T3	8		T6	1
all_pins[3]	339	1			T1	8		T3	8		T6	1
all_pins[4]	339	1			T1	8		T3	8		T6	1
all_pins[5]	339	1			T1	8		T3	8		T6	1
all_pins[6]	339	1			T1	8		T3	8		T6	1
all_pins[7]	339	1			T1	8		T3	8		T6	1
all_pins[8]	339	1			T1	8		T3	8		T6	1
all_pins[9]	339	1			T1	8		T3	8		T6	1
all_pins[10]	339	1			T1	8		T3	8		T6	1
all_pins[11]	339	1			T1	8		T3	8		T6	1
all_pins[12]	339	1			T1	8		T3	8		T6	1
all_pins[13]	339	1			T1	8		T3	8		T6	1
all_pins[14]	339	1			T1	8		T3	8		T6	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4244	1			T1	92		T3	98		T6	15
values[0x1]	841	1			T1	28		T3	22		T11	11
transitions[0x0=>0x1]	637	1			T1	23		T3	13		T11	10
transitions[0x1=>0x0]	644	1			T1	23		T3	13		T11	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286	1			T1	5		T3	7		T6	1
all_pins[0]	values[0x1]	53	1			T1	3		T3	1		T11	1
all_pins[0]	transitions[0x0=>0x1]	37	1			T1	2		T48	1		T49	1
all_pins[0]	transitions[0x1=>0x0]	41	1			T1	1		T3	1		T49	1
all_pins[1]	values[0x0]	282	1			T1	6		T3	6		T6	1
all_pins[1]	values[0x1]	57	1			T1	2		T3	2		T11	1
all_pins[1]	transitions[0x0=>0x1]	39	1			T1	1		T3	1		T11	1
all_pins[1]	transitions[0x1=>0x0]	38	1			T1	1		T12	1		T48	1
all_pins[2]	values[0x0]	283	1			T1	6		T3	7		T6	1
all_pins[2]	values[0x1]	56	1			T1	2		T3	1		T12	2
all_pins[2]	transitions[0x0=>0x1]	43	1			T1	1		T3	1		T12	2
all_pins[2]	transitions[0x1=>0x0]	41	1			T1	1		T3	2		T11	2
all_pins[3]	values[0x0]	285	1			T1	6		T3	6		T6	1
all_pins[3]	values[0x1]	54	1			T1	2		T3	2		T11	2
all_pins[3]	transitions[0x0=>0x1]	42	1			T1	1		T3	1		T11	2
all_pins[3]	transitions[0x1=>0x0]	38	1			T1	1		T12	1		T50	2
all_pins[4]	values[0x0]	289	1			T1	6		T3	7		T6	1
all_pins[4]	values[0x1]	50	1			T1	2		T3	1		T12	1
all_pins[4]	transitions[0x0=>0x1]	37	1			T1	2		T12	1		T50	2
all_pins[4]	transitions[0x1=>0x0]	32	1			T1	1		T11	1		T48	1
all_pins[5]	values[0x0]	294	1			T1	7		T3	7		T6	1
all_pins[5]	values[0x1]	45	1			T1	1		T3	1		T11	1
all_pins[5]	transitions[0x0=>0x1]	33	1			T1	1		T11	1		T37	1
all_pins[5]	transitions[0x1=>0x0]	62	1			T1	2		T3	4		T12	2
all_pins[6]	values[0x0]	265	1			T1	6		T3	3		T6	1
all_pins[6]	values[0x1]	74	1			T1	2		T3	5		T12	2
all_pins[6]	transitions[0x0=>0x1]	61	1			T1	2		T3	4		T12	2
all_pins[6]	transitions[0x1=>0x0]	49	1			T1	3		T3	1		T11	2
all_pins[7]	values[0x0]	277	1			T1	5		T3	6		T6	1
all_pins[7]	values[0x1]	62	1			T1	3		T3	2		T11	2
all_pins[7]	transitions[0x0=>0x1]	46	1			T1	3		T3	1		T11	2
all_pins[7]	transitions[0x1=>0x0]	46	1			T1	4		T11	1		T12	2
all_pins[8]	values[0x0]	277	1			T1	4		T3	7		T6	1
all_pins[8]	values[0x1]	62	1			T1	4		T3	1		T11	1
all_pins[8]	transitions[0x0=>0x1]	47	1			T1	4		T3	1		T11	1
all_pins[8]	transitions[0x1=>0x0]	42	1			T1	1		T3	2		T12	1
all_pins[9]	values[0x0]	282	1			T1	7		T3	6		T6	1
all_pins[9]	values[0x1]	57	1			T1	1		T3	2		T12	3
all_pins[9]	transitions[0x0=>0x1]	43	1			T1	1		T3	1		T12	3
all_pins[9]	transitions[0x1=>0x0]	35	1			T11	1		T12	1		T50	2
all_pins[10]	values[0x0]	290	1			T1	8		T3	7		T6	1
all_pins[10]	values[0x1]	49	1			T3	1		T11	1		T12	1
all_pins[10]	transitions[0x0=>0x1]	37	1			T3	1		T11	1		T50	1
all_pins[10]	transitions[0x1=>0x0]	44	1			T1	3		T3	1		T11	1
all_pins[11]	values[0x0]	283	1			T1	5		T3	7		T6	1
all_pins[11]	values[0x1]	56	1			T1	3		T3	1		T11	1
all_pins[11]	transitions[0x0=>0x1]	45	1			T1	2		T11	1		T12	2
all_pins[11]	transitions[0x1=>0x0]	37	1			T3	1		T11	1		T50	1
all_pins[12]	values[0x0]	291	1			T1	7		T3	6		T6	1
all_pins[12]	values[0x1]	48	1			T1	1		T3	2		T11	1
all_pins[12]	transitions[0x0=>0x1]	41	1			T1	1		T3	2		T11	1
all_pins[12]	transitions[0x1=>0x0]	57	1			T1	1		T48	2		T49	2
all_pins[13]	values[0x0]	275	1			T1	7		T3	8		T6	1
all_pins[13]	values[0x1]	64	1			T1	1		T48	2		T49	2
all_pins[13]	transitions[0x0=>0x1]	53	1			T1	1		T48	2		T49	1
all_pins[13]	transitions[0x1=>0x0]	43	1			T1	1		T12	1		T50	2
all_pins[14]	values[0x0]	285	1			T1	7		T3	8		T6	1
all_pins[14]	values[0x1]	54	1			T1	1		T12	1		T49	1
all_pins[14]	transitions[0x0=>0x1]	33	1			T1	1		T50	3		T38	2
all_pins[14]	transitions[0x1=>0x0]	39	1			T1	3		T3	1		T11	1