Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T1	7		T3	7		T11	4
all_values[1]	269	1			T1	7		T3	7		T11	4
all_values[2]	269	1			T1	7		T3	7		T11	4
all_values[3]	269	1			T1	7		T3	7		T11	4
all_values[4]	269	1			T1	7		T3	7		T11	4
all_values[5]	269	1			T1	7		T3	7		T11	4
all_values[6]	269	1			T1	7		T3	7		T11	4
all_values[7]	269	1			T1	7		T3	7		T11	4
all_values[8]	269	1			T1	7		T3	7		T11	4
all_values[9]	269	1			T1	7		T3	7		T11	4
all_values[10]	269	1			T1	7		T3	7		T11	4
all_values[11]	269	1			T1	7		T3	7		T11	4
all_values[12]	269	1			T1	7		T3	7		T11	4
all_values[13]	269	1			T1	7		T3	7		T11	4
all_values[14]	269	1			T1	7		T3	7		T11	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2244

1

T1

63

T3

59

T11

34

auto[1]

1791

1

T1

42

T3

46

T11

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

730

1

T1

11

T3

12

T11

14

auto[1]

3305

1

T1

94

T3

93

T11

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2419

1

T1

50

T3

64

T11

39

auto[1]

1616

1

T1

55

T3

41

T11

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1			T1	1		T3	1		T49	1
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T3	1		T11	1		T12	2
all_values[0]	auto[0]	auto[1]	auto[0]	12	1			T12	2		T50	2		T38	2
all_values[0]	auto[0]	auto[1]	auto[1]	55	1			T1	2		T3	2		T11	1
all_values[0]	auto[1]	auto[0]	auto[1]	52	1			T1	1		T3	3		T11	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1			T1	3		T11	1		T12	2
all_values[1]	auto[0]	auto[0]	auto[0]	23	1			T48	1		T49	1		T50	2
all_values[1]	auto[0]	auto[0]	auto[1]	62	1			T1	1		T3	2		T11	2
all_values[1]	auto[0]	auto[1]	auto[0]	11	1			T49	1		T40	2		T77	3
all_values[1]	auto[0]	auto[1]	auto[1]	56	1			T1	2		T3	2		T12	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1			T1	3		T3	2		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	54	1			T1	1		T3	1		T11	2
all_values[2]	auto[0]	auto[0]	auto[0]	28	1			T37	1		T38	3		T78	2
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T1	1		T3	3		T11	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1			T38	4		T42	2		T79	1
all_values[2]	auto[0]	auto[1]	auto[1]	53	1			T3	1		T12	1		T48	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T1	4		T3	1		T11	2
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T1	2		T3	2		T12	3
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T49	1		T38	4		T39	1
all_values[3]	auto[0]	auto[0]	auto[1]	58	1			T1	1		T3	2		T12	1
all_values[3]	auto[0]	auto[1]	auto[0]	13	1			T11	2		T39	2		T42	1
all_values[3]	auto[0]	auto[1]	auto[1]	58	1			T1	2		T3	3		T11	1
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T1	3		T3	1		T12	2
all_values[3]	auto[1]	auto[1]	auto[1]	45	1			T1	1		T3	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[0]	28	1			T49	1		T50	1		T37	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T1	3		T3	4		T11	3
all_values[4]	auto[0]	auto[1]	auto[0]	13	1			T79	1		T80	1		T81	1
all_values[4]	auto[0]	auto[1]	auto[1]	49	1			T12	1		T48	2		T49	1
all_values[4]	auto[1]	auto[0]	auto[1]	59	1			T1	2		T3	1		T11	1
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T1	2		T3	2		T50	1
all_values[5]	auto[0]	auto[0]	auto[0]	28	1			T1	1		T3	1		T11	1
all_values[5]	auto[0]	auto[0]	auto[1]	65	1			T1	3		T11	1		T12	1
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T1	1		T12	2		T38	1
all_values[5]	auto[0]	auto[1]	auto[1]	57	1			T3	2		T12	3		T50	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1			T1	2		T3	2		T11	2
all_values[5]	auto[1]	auto[1]	auto[1]	39	1			T3	2		T48	2		T37	3
all_values[6]	auto[0]	auto[0]	auto[0]	37	1			T1	4		T3	1		T49	4
all_values[6]	auto[0]	auto[0]	auto[1]	43	1			T12	1		T50	3		T38	3
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T11	1		T50	1		T42	2
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T1	2		T3	3		T11	2
all_values[6]	auto[1]	auto[0]	auto[1]	45	1			T3	1		T12	3		T48	1
all_values[6]	auto[1]	auto[1]	auto[1]	55	1			T1	1		T3	2		T11	1
all_values[7]	auto[0]	auto[0]	auto[0]	27	1			T48	1		T49	3		T39	1
all_values[7]	auto[0]	auto[0]	auto[1]	52	1			T1	2		T3	1		T12	2
all_values[7]	auto[0]	auto[1]	auto[0]	12	1			T49	1		T79	1		T82	1
all_values[7]	auto[0]	auto[1]	auto[1]	59	1			T1	2		T3	2		T11	1
all_values[7]	auto[1]	auto[0]	auto[1]	66	1			T1	1		T3	3		T11	2
all_values[7]	auto[1]	auto[1]	auto[1]	53	1			T1	2		T3	1		T11	1
all_values[8]	auto[0]	auto[0]	auto[0]	37	1			T49	2		T50	2		T38	1
all_values[8]	auto[0]	auto[0]	auto[1]	49	1			T1	1		T3	1		T11	2
all_values[8]	auto[0]	auto[1]	auto[0]	26	1			T49	2		T42	1		T79	1
all_values[8]	auto[0]	auto[1]	auto[1]	61	1			T1	1		T3	4		T12	2
all_values[8]	auto[1]	auto[0]	auto[1]	55	1			T1	3		T3	2		T11	2
all_values[8]	auto[1]	auto[1]	auto[1]	41	1			T1	2		T12	1		T50	1
all_values[9]	auto[0]	auto[0]	auto[0]	40	1			T1	1		T11	2		T49	3
all_values[9]	auto[0]	auto[0]	auto[1]	52	1			T1	2		T3	3		T11	1
all_values[9]	auto[0]	auto[1]	auto[0]	18	1			T1	1		T49	1		T39	2
all_values[9]	auto[0]	auto[1]	auto[1]	53	1			T3	1		T12	1		T48	1
all_values[9]	auto[1]	auto[0]	auto[1]	64	1			T3	2		T11	1		T12	2
all_values[9]	auto[1]	auto[1]	auto[1]	42	1			T1	3		T3	1		T12	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T1	1		T3	1		T11	2
all_values[10]	auto[0]	auto[0]	auto[1]	61	1			T1	2		T3	4		T12	2
all_values[10]	auto[0]	auto[1]	auto[0]	21	1			T12	2		T49	3		T37	1
all_values[10]	auto[0]	auto[1]	auto[1]	35	1			T11	1		T12	1		T50	1
all_values[10]	auto[1]	auto[0]	auto[1]	71	1			T1	3		T3	1		T12	1
all_values[10]	auto[1]	auto[1]	auto[1]	43	1			T1	1		T3	1		T11	1
all_values[11]	auto[0]	auto[0]	auto[0]	20	1			T48	1		T39	1		T79	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1			T1	1		T12	3		T49	1
all_values[11]	auto[0]	auto[1]	auto[0]	22	1			T3	3		T50	2		T40	4
all_values[11]	auto[0]	auto[1]	auto[1]	54	1			T1	1		T3	2		T11	3
all_values[11]	auto[1]	auto[0]	auto[1]	65	1			T1	4		T3	1		T49	1
all_values[11]	auto[1]	auto[1]	auto[1]	51	1			T1	1		T3	1		T11	1
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T1	1		T11	2		T49	2
all_values[12]	auto[0]	auto[0]	auto[1]	74	1			T1	2		T3	3		T12	2
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T50	1		T40	2		T83	2
all_values[12]	auto[0]	auto[1]	auto[1]	48	1			T1	1		T3	2		T11	1
all_values[12]	auto[1]	auto[0]	auto[1]	55	1			T1	2		T3	1		T12	3
all_values[12]	auto[1]	auto[1]	auto[1]	39	1			T1	1		T3	1		T11	1
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T3	1		T11	2		T48	2
all_values[13]	auto[0]	auto[0]	auto[1]	59	1			T1	1		T3	2		T12	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1			T11	2		T12	3		T40	2
all_values[13]	auto[0]	auto[1]	auto[1]	51	1			T1	2		T12	2		T48	1
all_values[13]	auto[1]	auto[0]	auto[1]	47	1			T1	3		T3	3		T48	1
all_values[13]	auto[1]	auto[1]	auto[1]	60	1			T1	1		T3	1		T12	1
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T3	1		T12	1		T37	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1			T1	1		T3	2		T11	1
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T3	3		T38	3		T39	1
all_values[14]	auto[0]	auto[1]	auto[1]	46	1			T1	3		T11	2		T12	1
all_values[14]	auto[1]	auto[0]	auto[1]	62	1			T1	2		T3	1		T11	1
all_values[14]	auto[1]	auto[1]	auto[1]	44	1			T1	1		T48	1		T50	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal