Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	400133860	0	0	0
ctrl_rd_A	400133860	2009	0	0
host_fifo_config_rd_A	400133860	2772	0	0
host_nack_handler_timeout_rd_A	400133860	1336	0	0
host_timeout_ctrl_rd_A	400133860	1093	0	0
intr_enable_rd_A	400133860	3808	0	0
ovrd_rd_A	400133860	2181	0	0
target_fifo_config_rd_A	400133860	1312	0	0
target_id_rd_A	400133860	1477	0	0
target_timeout_ctrl_rd_A	400133860	1226	0	0
timeout_ctrl_rd_A	400133860	1445	0	0
timing0_rd_A	400133860	1304	0	0
timing1_rd_A	400133860	1356	0	0
timing2_rd_A	400133860	1193	0	0
timing3_rd_A	400133860	1246	0	0
timing4_rd_A	400133860	1378	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	2009	0	0
T95	14981	27	0	0
T96	6838	127	0	0
T97	12410	12	0	0
T98	14161	277	0	0
T99	7010	13	0	0
T100	1219	5	0	0
T101	1650	4	0	0
T102	1455	15	0	0
T103	2141	7	0	0
T104	2257	3	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	2772	0	0
T25	52471	0	0	0
T28	0	139	0	0
T78	787369	0	0	0
T79	102391	0	0	0
T105	513463	161	0	0
T106	0	128	0	0
T107	0	111	0	0
T108	0	151	0	0
T109	0	130	0	0
T110	0	110	0	0
T111	0	131	0	0
T112	0	123	0	0
T113	0	66	0	0
T114	45130	0	0	0
T115	18234	0	0	0
T116	30108	0	0	0
T117	7067	0	0	0
T118	99372	0	0	0
T119	45463	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1336	0	0
T95	14981	7	0	0
T96	6838	30	0	0
T97	12410	36	0	0
T98	14161	121	0	0
T99	7010	8	0	0
T100	1219	12	0	0
T101	1650	6	0	0
T102	1455	1	0	0
T103	2141	9	0	0
T104	2257	18	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1093	0	0
T95	14981	14	0	0
T96	6838	18	0	0
T97	12410	16	0	0
T98	14161	84	0	0
T99	7010	29	0	0
T100	1219	7	0	0
T101	1650	2	0	0
T102	1455	9	0	0
T103	2141	4	0	0
T104	2257	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	3808	0	0
T95	0	61	0	0
T96	0	168	0	0
T97	0	23	0	0
T120	557314	59	0	0
T121	0	13	0	0
T122	0	8	0	0
T123	0	14	0	0
T124	0	13	0	0
T125	0	19	0	0
T126	0	19	0	0
T127	57087	0	0	0
T128	119289	0	0	0
T129	59869	0	0	0
T130	14598	0	0	0
T131	73527	0	0	0
T132	13136	0	0	0
T133	173814	0	0	0
T134	325337	0	0	0
T135	12700	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	2181	0	0
T16	632544	0	0	0
T55	52123	0	0	0
T56	59217	0	0	0
T57	51114	0	0	0
T64	126171	0	0	0
T73	38009	0	0	0
T92	1807	31	0	0
T136	0	19	0	0
T137	0	14	0	0
T138	0	37	0	0
T139	0	47	0	0
T140	0	59	0	0
T141	0	75	0	0
T142	0	55	0	0
T143	0	60	0	0
T144	0	37	0	0
T145	139241	0	0	0
T146	60062	0	0	0
T147	35360	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1312	0	0
T95	14981	31	0	0
T96	6838	40	0	0
T97	12410	48	0	0
T98	14161	97	0	0
T99	7010	14	0	0
T100	1219	4	0	0
T101	1650	5	0	0
T103	2141	7	0	0
T104	2257	12	0	0
T148	5646	50	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1477	0	0
T95	14981	21	0	0
T96	6838	45	0	0
T97	12410	15	0	0
T98	14161	166	0	0
T99	7010	20	0	0
T100	1219	19	0	0
T101	1650	10	0	0
T103	2141	10	0	0
T104	2257	13	0	0
T148	5646	16	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1226	0	0
T95	14981	11	0	0
T96	6838	31	0	0
T97	12410	43	0	0
T98	14161	95	0	0
T99	7010	2	0	0
T100	1219	2	0	0
T101	1650	2	0	0
T103	2141	7	0	0
T104	2257	5	0	0
T148	5646	42	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1445	0	0
T95	14981	21	0	0
T96	6838	45	0	0
T97	12410	28	0	0
T98	14161	134	0	0
T99	7010	7	0	0
T100	1219	2	0	0
T101	1650	3	0	0
T102	1455	15	0	0
T103	2141	8	0	0
T104	2257	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1304	0	0
T95	14981	16	0	0
T96	6838	31	0	0
T97	12410	42	0	0
T98	14161	104	0	0
T99	7010	16	0	0
T100	1219	7	0	0
T101	1650	3	0	0
T102	1455	7	0	0
T103	2141	10	0	0
T104	2257	12	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1356	0	0
T95	14981	28	0	0
T96	6838	15	0	0
T97	12410	22	0	0
T98	14161	123	0	0
T99	7010	21	0	0
T100	1219	7	0	0
T101	1650	6	0	0
T102	1455	10	0	0
T103	2141	35	0	0
T104	2257	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1193	0	0
T95	14981	22	0	0
T96	6838	43	0	0
T97	12410	55	0	0
T98	14161	125	0	0
T99	7010	21	0	0
T100	1219	5	0	0
T101	1650	7	0	0
T102	1455	10	0	0
T103	2141	9	0	0
T104	2257	5	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1246	0	0
T95	14981	12	0	0
T96	6838	52	0	0
T97	12410	24	0	0
T98	14161	111	0	0
T99	7010	7	0	0
T100	1219	12	0	0
T101	1650	5	0	0
T103	2141	22	0	0
T104	2257	5	0	0
T148	5646	20	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400133860	1378	0	0
T95	14981	29	0	0
T96	6838	30	0	0
T97	12410	24	0	0
T98	14161	111	0	0
T99	7010	23	0	0
T100	1219	3	0	0
T101	1650	10	0	0
T103	2141	18	0	0
T104	2257	8	0	0
T148	5646	37	0	0