Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27547427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7416230

1

T1

446

T2

192

T3

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34202915	1			T1	1236		T2	25783		T3	9112
values[0x0]	380105	1			T1	66		T2	108		T3	42
values[0x1]	380637	1			T1	64		T2	107		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19285105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15678552

1

T1

656

T2

12984

T3

2337

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	131985	1			T1	3		T3	32		T5	1
valid_sources[0x01]	134150	1			T1	9		T3	34		T5	1
valid_sources[0x02]	125007	1			T1	5		T3	32		T6	95
valid_sources[0x03]	138548	1			T1	11		T3	29		T5	3
valid_sources[0x04]	127680	1			T1	1		T3	40		T6	118
valid_sources[0x05]	135628	1			T1	2		T3	32		T4	4
valid_sources[0x06]	129329	1			T1	10		T3	36		T6	92
valid_sources[0x07]	137308	1			T1	6		T3	32		T4	2
valid_sources[0x08]	147070	1			T1	14		T3	41		T5	1
valid_sources[0x09]	147845	1			T1	2		T3	34		T4	10
valid_sources[0x0a]	129859	1			T1	4		T3	38		T5	2
valid_sources[0x0b]	130584	1			T1	2		T3	57		T5	2
valid_sources[0x0c]	135757	1			T1	8		T3	34		T4	19
valid_sources[0x0d]	131032	1			T1	5		T3	33		T4	9
valid_sources[0x0e]	134064	1			T1	3		T3	36		T6	116
valid_sources[0x0f]	135510	1			T1	3		T3	30		T4	4
valid_sources[0x10]	141942	1			T1	5		T3	37		T4	9
valid_sources[0x11]	129267	1			T1	6		T3	32		T4	2
valid_sources[0x12]	133885	1			T1	5		T3	32		T4	3
valid_sources[0x13]	129715	1			T1	2		T3	33		T5	1
valid_sources[0x14]	137122	1			T1	9		T3	30		T4	15
valid_sources[0x15]	138134	1			T1	1		T3	32		T4	10
valid_sources[0x16]	132951	1			T1	5		T3	31		T4	2
valid_sources[0x17]	133353	1			T1	3		T3	38		T4	5
valid_sources[0x18]	189856	1			T1	4		T3	30		T5	2
valid_sources[0x19]	127352	1			T1	16		T3	48		T4	25
valid_sources[0x1a]	122583	1			T1	4		T3	43		T6	92
valid_sources[0x1b]	130678	1			T1	5		T3	41		T4	3
valid_sources[0x1c]	137081	1			T1	2		T3	28		T4	5
valid_sources[0x1d]	145802	1			T1	6		T3	37		T4	5
valid_sources[0x1e]	142951	1			T1	7		T3	37		T4	6
valid_sources[0x1f]	150158	1			T1	12		T3	35		T4	18
valid_sources[0x20]	137518	1			T1	6		T2	5679		T3	25
valid_sources[0x21]	135397	1			T1	2		T3	41		T4	11
valid_sources[0x22]	123430	1			T1	5		T3	42		T6	111
valid_sources[0x23]	135565	1			T1	9		T3	35		T6	89
valid_sources[0x24]	132902	1			T1	5		T3	31		T6	148
valid_sources[0x25]	155410	1			T1	5		T3	34		T4	8
valid_sources[0x26]	132351	1			T1	8		T3	40		T4	1
valid_sources[0x27]	136130	1			T1	6		T3	37		T4	18
valid_sources[0x28]	147243	1			T1	5		T3	30		T5	8
valid_sources[0x29]	137114	1			T1	5		T3	28		T4	14
valid_sources[0x2a]	130195	1			T1	1		T3	44		T4	2
valid_sources[0x2b]	135224	1			T1	6		T3	31		T4	4
valid_sources[0x2c]	144347	1			T1	7		T3	32		T5	1
valid_sources[0x2d]	126764	1			T1	2		T3	40		T5	2
valid_sources[0x2e]	161341	1			T1	7		T3	40		T4	8
valid_sources[0x2f]	133338	1			T1	5		T3	43		T4	1
valid_sources[0x30]	123183	1			T1	4		T3	27		T4	5
valid_sources[0x31]	133457	1			T1	10		T3	53		T6	110
valid_sources[0x32]	146030	1			T1	3		T3	37		T6	129
valid_sources[0x33]	138236	1			T1	5		T3	32		T4	2
valid_sources[0x34]	137374	1			T1	7		T3	30		T6	132
valid_sources[0x35]	124153	1			T1	1		T3	39		T4	46
valid_sources[0x36]	140408	1			T1	4		T3	34		T6	118
valid_sources[0x37]	133292	1			T1	3		T3	44		T4	3
valid_sources[0x38]	126719	1			T1	8		T3	33		T5	1
valid_sources[0x39]	136839	1			T1	2		T3	41		T4	9
valid_sources[0x3a]	127705	1			T1	2		T3	33		T5	3
valid_sources[0x3b]	134561	1			T1	4		T3	36		T6	137
valid_sources[0x3c]	129388	1			T1	11		T3	40		T5	1
valid_sources[0x3d]	133619	1			T1	8		T3	38		T6	135
valid_sources[0x3e]	124590	1			T1	4		T3	33		T4	9
valid_sources[0x3f]	139444	1			T1	3		T3	37		T6	94
valid_sources[0x40]	134938	1			T1	3		T3	28		T4	1
valid_sources[0x41]	149924	1			T1	7		T3	38		T4	14
valid_sources[0x42]	153500	1			T1	6		T3	40		T5	2
valid_sources[0x43]	130696	1			T1	5		T3	26		T4	10
valid_sources[0x44]	133849	1			T1	6		T3	37		T5	2
valid_sources[0x45]	163444	1			T1	13		T3	35		T4	11
valid_sources[0x46]	125559	1			T1	3		T3	16		T4	8
valid_sources[0x47]	136884	1			T1	2		T3	38		T5	3
valid_sources[0x48]	148987	1			T1	3		T3	30		T4	8
valid_sources[0x49]	160855	1			T1	3		T3	32		T4	11
valid_sources[0x4a]	126309	1			T1	11		T3	45		T5	1
valid_sources[0x4b]	139659	1			T1	3		T3	37		T5	3
valid_sources[0x4c]	135408	1			T1	6		T3	43		T4	18
valid_sources[0x4d]	145335	1			T1	3		T3	34		T5	1
valid_sources[0x4e]	137162	1			T1	6		T3	41		T6	98
valid_sources[0x4f]	123538	1			T1	2		T3	46		T5	1
valid_sources[0x50]	148400	1			T1	5		T3	36		T4	2
valid_sources[0x51]	145574	1			T1	3		T3	40		T4	5
valid_sources[0x52]	145841	1			T1	2		T3	40		T5	5
valid_sources[0x53]	129463	1			T1	3		T3	32		T4	5
valid_sources[0x54]	158220	1			T1	1		T3	28		T6	105
valid_sources[0x55]	135028	1			T1	6		T3	32		T4	6
valid_sources[0x56]	137441	1			T1	8		T3	38		T5	1
valid_sources[0x57]	127745	1			T1	7		T3	29		T6	119
valid_sources[0x58]	139404	1			T1	2		T3	35		T6	128
valid_sources[0x59]	134459	1			T1	3		T3	33		T4	4
valid_sources[0x5a]	138982	1			T1	6		T3	37		T4	16
valid_sources[0x5b]	146268	1			T1	11		T3	44		T4	3
valid_sources[0x5c]	141406	1			T1	4		T3	48		T6	128
valid_sources[0x5d]	137359	1			T1	8		T3	33		T4	9
valid_sources[0x5e]	143595	1			T1	4		T3	40		T6	125
valid_sources[0x5f]	145913	1			T1	8		T3	36		T4	6
valid_sources[0x60]	132491	1			T1	14		T3	39		T5	3
valid_sources[0x61]	142850	1			T1	9		T3	37		T4	2
valid_sources[0x62]	140279	1			T1	2		T3	43		T5	1
valid_sources[0x63]	130206	1			T1	5		T3	37		T5	4
valid_sources[0x64]	156487	1			T1	6		T3	28		T4	2
valid_sources[0x65]	137908	1			T1	6		T3	45		T6	104
valid_sources[0x66]	131494	1			T1	5		T3	49		T5	1
valid_sources[0x67]	136691	1			T1	1		T3	42		T6	117
valid_sources[0x68]	145404	1			T1	1		T3	30		T4	5
valid_sources[0x69]	130507	1			T1	7		T3	27		T5	1
valid_sources[0x6a]	138597	1			T1	6		T2	86		T3	29
valid_sources[0x6b]	130912	1			T1	5		T3	47		T5	3
valid_sources[0x6c]	142210	1			T1	6		T3	29		T5	2
valid_sources[0x6d]	127318	1			T1	10		T3	23		T5	2
valid_sources[0x6e]	137852	1			T1	5		T3	38		T5	3
valid_sources[0x6f]	141593	1			T1	1		T2	4		T3	49
valid_sources[0x70]	132786	1			T1	10		T3	32		T4	6
valid_sources[0x71]	139250	1			T1	14		T3	46		T4	6
valid_sources[0x72]	135371	1			T1	5		T3	28		T5	1
valid_sources[0x73]	130702	1			T1	8		T3	31		T4	15
valid_sources[0x74]	135467	1			T1	9		T3	30		T4	2
valid_sources[0x75]	136465	1			T3	46		T4	6		T6	99
valid_sources[0x76]	126849	1			T1	5		T3	41		T4	7
valid_sources[0x77]	129933	1			T1	3		T3	38		T6	124
valid_sources[0x78]	144317	1			T1	1		T3	27		T5	1
valid_sources[0x79]	147623	1			T1	5		T3	26		T6	113
valid_sources[0x7a]	132188	1			T1	5		T3	28		T4	3
valid_sources[0x7b]	132801	1			T1	2		T3	32		T4	1
valid_sources[0x7c]	140345	1			T1	4		T3	39		T6	107
valid_sources[0x7d]	145264	1			T1	7		T3	36		T6	152
valid_sources[0x7e]	134947	1			T1	4		T3	31		T4	5
valid_sources[0x7f]	146117	1			T1	3		T3	27		T5	1
valid_sources[0x80]	134857	1			T1	2		T3	31		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7077117

1

T1

347

T2

122

T3

11

values[0x0]

all_enables

biggest_size

200883

1

T1

52

T2

45

T3

18

values[0x1]

all_enables

biggest_size

138230

1

T1

47

T2

25

T3

13