Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_stretch_cg

Group : i2c_env_pkg::i2c_scl_stretch_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
40.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	3	3	50.00
Crosses	4	3	1	25.00

Variables for Group i2c_env_pkg::i2c_scl_stretch_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_fifo_size	2	1	1	50.00	100	1	1	0
cp_host_mode_stretch	1	1	0	0.00	100	1	1	0
cp_target_scl_stretch_addr_write	1	1	0	0.00	100	1	1	0
cp_tx_fifo_size	2	0	2	100.00	100	1	1	0

Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_target_scl_stretch_read	4	3	1	25.00	100	1	1	0

Summary for Variable cp_acq_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_acq_fifo_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
not_empty	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

13355

1

T5

212

T7

32

T9

159

---

Summary for Variable cp_host_mode_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_host_mode_stretch

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
stretch	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded

---

Summary for Variable cp_target_scl_stretch_addr_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_target_scl_stretch_addr_write

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
addr_write_byte_stretch	0	1	1

---

Summary for Variable cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_tx_fifo_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
not_empty	25	1			T57	25		-	-		-	-
empty	13330	1			T5	212		T7	32		T9	159

---

Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	3	1	25.00	1
Automatically Generated Cross Bins	2	1	1	50.00	1
User Defined Cross Bins	2	2	0	0.00

Automatically Generated Cross Bins for cp_target_scl_stretch_read

Uncovered bins

cp_acq_fifo_size	cp_tx_fifo_size	COUNT	AT LEAST	NUMBER	STATUS
[empty]	[not_empty]	0	1	1

Covered bins

cp_acq_fifo_size

cp_tx_fifo_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

empty

2321

1

T5

212

T7

11

T9

119

User Defined Cross Bins for cp_target_scl_stretch_read

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_byte_stretch	0	1	1
scl_stretch_read_request	0	1	1