| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 52.60 | 40.66 | 40.72 | 90.72 | 0.00 | 42.98 | 99.68 | 53.47 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 45.85 | 45.85 | 39.00 | 39.00 | 37.11 | 37.11 | 92.56 | 92.56 | 0.00 | 0.00 | 41.70 | 41.70 | 91.72 | 91.72 | 18.84 | 18.84 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1869110211 |
| 50.75 | 4.90 | 40.20 | 1.19 | 39.29 | 2.18 | 95.53 | 2.98 | 0.00 | 0.00 | 42.84 | 1.13 | 92.04 | 0.32 | 45.37 | 26.53 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.929902618 |
| 52.02 | 1.26 | 40.20 | 0.00 | 40.16 | 0.87 | 96.77 | 1.24 | 0.00 | 0.00 | 42.91 | 0.07 | 96.82 | 4.78 | 47.26 | 1.89 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2306116177 |
| 52.49 | 0.47 | 40.20 | 0.00 | 40.16 | 0.00 | 97.02 | 0.25 | 0.00 | 0.00 | 42.91 | 0.00 | 96.82 | 0.00 | 50.32 | 3.05 | /workspace/coverage/cover_reg_top/3.i2c_intr_test.422930549 |
| 52.89 | 0.40 | 40.66 | 0.46 | 40.27 | 0.11 | 97.02 | 0.00 | 0.00 | 0.00 | 42.91 | 0.00 | 99.04 | 2.23 | 50.32 | 0.00 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1423653971 |
| 53.05 | 0.16 | 40.66 | 0.00 | 40.27 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.07 | 99.36 | 0.32 | 51.05 | 0.74 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1649658778 |
| 53.20 | 0.15 | 40.66 | 0.00 | 40.27 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.36 | 0.00 | 52.11 | 1.05 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2499278923 |
| 53.29 | 0.09 | 40.66 | 0.00 | 40.27 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.36 | 0.00 | 52.74 | 0.63 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.2157647820 |
| 53.37 | 0.08 | 40.66 | 0.00 | 40.27 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.32 | 52.95 | 0.21 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2949318811 |
| 53.40 | 0.04 | 40.66 | 0.00 | 40.42 | 0.15 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.05 | 0.11 | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3503016143 |
| 53.43 | 0.03 | 40.66 | 0.00 | 40.53 | 0.11 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.16 | 0.11 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.905360944 |
| 53.46 | 0.03 | 40.66 | 0.00 | 40.53 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.37 | 0.21 | /workspace/coverage/cover_reg_top/0.i2c_intr_test.4221878468 |
| 53.48 | 0.02 | 40.66 | 0.00 | 40.53 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.47 | 0.11 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3941918516 |
| 53.49 | 0.01 | 40.66 | 0.00 | 40.61 | 0.08 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.47 | 0.00 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2557967283 |
| 53.49 | 0.01 | 40.66 | 0.00 | 40.65 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.47 | 0.00 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1961000203 |
| 53.50 | 0.01 | 40.66 | 0.00 | 40.68 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.47 | 0.00 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2854674881 |
| 53.50 | 0.01 | 40.66 | 0.00 | 40.72 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.47 | 0.00 | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1642253927 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.906104134 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3972517416 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4052940461 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2462723013 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3472892318 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3228030593 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.837198380 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.260906451 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1199461069 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.1370892858 |
| /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2829787473 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1912030162 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.761082739 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3220282720 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1383832505 |
| /workspace/coverage/cover_reg_top/10.i2c_intr_test.3411814389 |
| /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2306188416 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2573907128 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1736011707 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2652775446 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.3672090708 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.66114146 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1180336125 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.718544292 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2242434718 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.1760233567 |
| /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3081406506 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3490310125 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2482646832 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.157114196 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1443401894 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.421071619 |
| /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.520199584 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1283778828 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1892349781 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3797192580 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2259507457 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.586615710 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.62536444 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2111217559 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1749225730 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3834299576 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.387613555 |
| /workspace/coverage/cover_reg_top/15.i2c_intr_test.4105973870 |
| /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1476321621 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_errors.911415082 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.933492833 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3665550522 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3896580275 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.2302296717 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1223226954 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.344479290 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.977035149 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.618983940 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2421920402 |
| /workspace/coverage/cover_reg_top/17.i2c_intr_test.2801942632 |
| /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.924696371 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1098915734 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1149166038 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1798896825 |
| /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2764497258 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.224986750 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2140394247 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1825028778 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2327086959 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.2781071117 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1024205241 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_errors.283985657 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1220261460 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2663580412 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2671771699 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1859232316 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3926360997 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.3701560210 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3989393649 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_errors.684975347 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2271024723 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.3592192292 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.1662837624 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.4024273772 |
| /workspace/coverage/cover_reg_top/24.i2c_intr_test.801419948 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.1980500743 |
| /workspace/coverage/cover_reg_top/26.i2c_intr_test.1635037462 |
| /workspace/coverage/cover_reg_top/27.i2c_intr_test.3402362712 |
| /workspace/coverage/cover_reg_top/28.i2c_intr_test.4240842006 |
| /workspace/coverage/cover_reg_top/29.i2c_intr_test.1360555147 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3670831800 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1457560710 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2415258538 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1051652242 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3219081549 |
| /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2695701158 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2966076945 |
| /workspace/coverage/cover_reg_top/30.i2c_intr_test.1418149112 |
| /workspace/coverage/cover_reg_top/31.i2c_intr_test.364862684 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.2087246659 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.1215115365 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.1665206141 |
| /workspace/coverage/cover_reg_top/35.i2c_intr_test.2164606401 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.441470986 |
| /workspace/coverage/cover_reg_top/37.i2c_intr_test.847340343 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.257575688 |
| /workspace/coverage/cover_reg_top/39.i2c_intr_test.2405840885 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2007325372 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1256304944 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.725819265 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.725628590 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2439681471 |
| /workspace/coverage/cover_reg_top/4.i2c_intr_test.1033946881 |
| /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1725094277 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4212155303 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.960611340 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.1898631936 |
| /workspace/coverage/cover_reg_top/43.i2c_intr_test.2735900869 |
| /workspace/coverage/cover_reg_top/44.i2c_intr_test.1062332374 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.1128938678 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.2128107696 |
| /workspace/coverage/cover_reg_top/47.i2c_intr_test.432680729 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.344671240 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.3218894403 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1448440039 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3575271572 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.2798753027 |
| /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.429158572 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1145444347 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2233245155 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2919192547 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3148733931 |
| /workspace/coverage/cover_reg_top/6.i2c_intr_test.3961217196 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4203321605 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4225660680 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2369655494 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2273152976 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.3491316152 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.578815336 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2277777137 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.437588546 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2964366829 |
| /workspace/coverage/cover_reg_top/8.i2c_intr_test.305398492 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.535496111 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1373429207 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1473395728 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3984555022 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1226876234 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.1345560403 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4110430096 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2044889574 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2482646832 | Aug 19 04:25:35 PM PDT 24 | Aug 19 04:25:37 PM PDT 24 | 123066412 ps | ||
| T2 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1725094277 | Aug 19 04:25:21 PM PDT 24 | Aug 19 04:25:22 PM PDT 24 | 28993504 ps | ||
| T3 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1869110211 | Aug 19 04:25:29 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 87840515 ps | ||
| T5 | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3672090708 | Aug 19 04:25:49 PM PDT 24 | Aug 19 04:25:50 PM PDT 24 | 18995185 ps | ||
| T7 | /workspace/coverage/cover_reg_top/25.i2c_intr_test.1980500743 | Aug 19 04:25:51 PM PDT 24 | Aug 19 04:25:52 PM PDT 24 | 38871689 ps | ||
| T6 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1749225730 | Aug 19 04:25:33 PM PDT 24 | Aug 19 04:25:35 PM PDT 24 | 286596924 ps | ||
| T11 | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.535496111 | Aug 19 04:25:31 PM PDT 24 | Aug 19 04:25:32 PM PDT 24 | 64095973 ps | ||
| T12 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1649658778 | Aug 19 04:25:26 PM PDT 24 | Aug 19 04:25:27 PM PDT 24 | 333848849 ps | ||
| T4 | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2111217559 | Aug 19 04:25:32 PM PDT 24 | Aug 19 04:25:33 PM PDT 24 | 127604413 ps | ||
| T13 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2306188416 | Aug 19 04:25:26 PM PDT 24 | Aug 19 04:25:27 PM PDT 24 | 42861569 ps | ||
| T21 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.906104134 | Aug 19 04:25:17 PM PDT 24 | Aug 19 04:25:19 PM PDT 24 | 29252461 ps | ||
| T22 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2829787473 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:17 PM PDT 24 | 69130592 ps | ||
| T14 | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.344479290 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:32 PM PDT 24 | 464589043 ps | ||
| T9 | /workspace/coverage/cover_reg_top/38.i2c_intr_test.257575688 | Aug 19 04:25:36 PM PDT 24 | Aug 19 04:25:37 PM PDT 24 | 143731691 ps | ||
| T15 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.578815336 | Aug 19 04:25:27 PM PDT 24 | Aug 19 04:25:28 PM PDT 24 | 62775718 ps | ||
| T16 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1961000203 | Aug 19 04:25:21 PM PDT 24 | Aug 19 04:25:23 PM PDT 24 | 142729489 ps | ||
| T26 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.933492833 | Aug 19 04:25:31 PM PDT 24 | Aug 19 04:25:32 PM PDT 24 | 43811149 ps | ||
| T8 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.929902618 | Aug 19 04:25:32 PM PDT 24 | Aug 19 04:25:32 PM PDT 24 | 18705430 ps | ||
| T23 | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2277777137 | Aug 19 04:25:32 PM PDT 24 | Aug 19 04:25:33 PM PDT 24 | 127730154 ps | ||
| T17 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.618983940 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 112674496 ps | ||
| T41 | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2273152976 | Aug 19 04:25:44 PM PDT 24 | Aug 19 04:25:44 PM PDT 24 | 135136935 ps | ||
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| T19 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.437588546 | Aug 19 04:25:27 PM PDT 24 | Aug 19 04:25:28 PM PDT 24 | 89857689 ps | ||
| T28 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1423653971 | Aug 19 04:25:19 PM PDT 24 | Aug 19 04:25:20 PM PDT 24 | 106824350 ps | ||
| T33 | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.62536444 | Aug 19 04:25:27 PM PDT 24 | Aug 19 04:25:28 PM PDT 24 | 61560379 ps | ||
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| T30 | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1256304944 | Aug 19 04:25:17 PM PDT 24 | Aug 19 04:25:22 PM PDT 24 | 1926872525 ps | ||
| T31 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2949318811 | Aug 19 04:25:21 PM PDT 24 | Aug 19 04:25:22 PM PDT 24 | 63520995 ps | ||
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| T42 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.429158572 | Aug 19 04:25:19 PM PDT 24 | Aug 19 04:25:21 PM PDT 24 | 77315640 ps | ||
| T43 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4110430096 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 35518670 ps | ||
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| T45 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3220282720 | Aug 19 04:25:28 PM PDT 24 | Aug 19 04:25:30 PM PDT 24 | 346128653 ps | ||
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| T77 | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1223226954 | Aug 19 04:25:44 PM PDT 24 | Aug 19 04:25:46 PM PDT 24 | 133986782 ps | ||
| T78 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.224986750 | Aug 19 04:25:44 PM PDT 24 | Aug 19 04:25:47 PM PDT 24 | 157838499 ps | ||
| T79 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1457560710 | Aug 19 04:25:18 PM PDT 24 | Aug 19 04:25:22 PM PDT 24 | 226836232 ps | ||
| T80 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.725819265 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:16 PM PDT 24 | 21883049 ps | ||
| T81 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1859232316 | Aug 19 04:25:19 PM PDT 24 | Aug 19 04:25:20 PM PDT 24 | 34947604 ps | ||
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| T83 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3989393649 | Aug 19 04:25:18 PM PDT 24 | Aug 19 04:25:19 PM PDT 24 | 62824835 ps | ||
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| T85 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1024205241 | Aug 19 04:25:25 PM PDT 24 | Aug 19 04:25:26 PM PDT 24 | 223002123 ps | ||
| T86 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.924696371 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 109362840 ps | ||
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| T37 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2663580412 | Aug 19 04:25:18 PM PDT 24 | Aug 19 04:25:20 PM PDT 24 | 38546245 ps | ||
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| T93 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1825028778 | Aug 19 04:25:56 PM PDT 24 | Aug 19 04:25:58 PM PDT 24 | 65807292 ps | ||
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| T110 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3670831800 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:18 PM PDT 24 | 86415096 ps | ||
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| T113 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3984555022 | Aug 19 04:25:28 PM PDT 24 | Aug 19 04:25:29 PM PDT 24 | 35422102 ps | ||
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| T144 | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2695701158 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:18 PM PDT 24 | 85442347 ps | ||
| T145 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2671771699 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:19 PM PDT 24 | 1182292427 ps | ||
| T47 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.905360944 | Aug 19 04:25:16 PM PDT 24 | Aug 19 04:25:17 PM PDT 24 | 115069253 ps | ||
| T146 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3665550522 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 39731859 ps | ||
| T147 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2415258538 | Aug 19 04:25:17 PM PDT 24 | Aug 19 04:25:18 PM PDT 24 | 79030827 ps | ||
| T148 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1283778828 | Aug 19 04:25:34 PM PDT 24 | Aug 19 04:25:36 PM PDT 24 | 61405686 ps | ||
| T149 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1220261460 | Aug 19 04:25:28 PM PDT 24 | Aug 19 04:25:29 PM PDT 24 | 258419460 ps | ||
| T150 | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.718544292 | Aug 19 04:25:38 PM PDT 24 | Aug 19 04:25:40 PM PDT 24 | 60928339 ps | ||
| T151 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3490310125 | Aug 19 04:25:30 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 246671140 ps | ||
| T152 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1373429207 | Aug 19 04:25:37 PM PDT 24 | Aug 19 04:25:39 PM PDT 24 | 57704725 ps | ||
| T153 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.847340343 | Aug 19 04:25:56 PM PDT 24 | Aug 19 04:25:57 PM PDT 24 | 54491273 ps | ||
| T154 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.725628590 | Aug 19 04:25:18 PM PDT 24 | Aug 19 04:25:19 PM PDT 24 | 55206692 ps | ||
| T155 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.684975347 | Aug 19 04:25:17 PM PDT 24 | Aug 19 04:25:19 PM PDT 24 | 151543923 ps | ||
| T156 | /workspace/coverage/cover_reg_top/21.i2c_intr_test.3592192292 | Aug 19 04:25:37 PM PDT 24 | Aug 19 04:25:38 PM PDT 24 | 19690910 ps | ||
| T157 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.837198380 | Aug 19 04:25:19 PM PDT 24 | Aug 19 04:25:20 PM PDT 24 | 37635682 ps | ||
| T158 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.421071619 | Aug 19 04:25:25 PM PDT 24 | Aug 19 04:25:31 PM PDT 24 | 18762213 ps | ||
| T159 | /workspace/coverage/cover_reg_top/32.i2c_intr_test.2087246659 | Aug 19 04:25:56 PM PDT 24 | Aug 19 04:25:57 PM PDT 24 | 62503579 ps | ||
| T160 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3926360997 | Aug 19 04:25:21 PM PDT 24 | Aug 19 04:25:21 PM PDT 24 | 19780055 ps | ||
| T161 | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2652775446 | Aug 19 04:25:26 PM PDT 24 | Aug 19 04:25:27 PM PDT 24 | 23808188 ps | ||
| T162 | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1798896825 | Aug 19 04:25:40 PM PDT 24 | Aug 19 04:25:41 PM PDT 24 | 54104231 ps | ||
| T163 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1383832505 | Aug 19 04:25:33 PM PDT 24 | Aug 19 04:25:34 PM PDT 24 | 56899984 ps | ||
| T164 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.364862684 | Aug 19 04:25:36 PM PDT 24 | Aug 19 04:25:37 PM PDT 24 | 15791257 ps |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1869110211 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 87840515 ps |
| CPU time | 2.02 seconds |
| Started | Aug 19 04:25:29 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-06e547a9-00ab-4a9a-b51c-337b84735ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869110211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1869110211 |
| Directory | /workspace/9.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.929902618 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 18705430 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204232 kb |
| Host | smart-2a16c5ef-9377-475e-9099-86ac10cb750d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929902618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.929902618 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2306116177 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1474271903 ps |
| CPU time | 2.66 seconds |
| Started | Aug 19 04:25:20 PM PDT 24 |
| Finished | Aug 19 04:25:23 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-03c4c8e0-10bc-42fd-8cf3-1abbdcbba557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306116177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2306116177 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.422930549 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26294859 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-34594506-6a28-4019-848d-89e6dd00d0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422930549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.422930549 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1423653971 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 106824350 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-084ecbc9-4df2-449e-9d47-2ea376ee6425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423653971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1423653971 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1649658778 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 333848849 ps |
| CPU time | 1.09 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:27 PM PDT 24 |
| Peak memory | 204596 kb |
| Host | smart-5ae22f89-8aa1-4325-b6fc-57be431150c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649658778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.1649658778 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2499278923 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 18544226 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:26:15 PM PDT 24 |
| Finished | Aug 19 04:26:16 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-f173dcdd-ffbf-4c87-a5db-5aed84a76019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499278923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2499278923 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.2157647820 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 57078226 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:54 PM PDT 24 |
| Finished | Aug 19 04:25:55 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-f82e8954-6eac-4730-ad6b-acd942916bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157647820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2157647820 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2949318811 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 63520995 ps |
| CPU time | 1.27 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-43977695-b507-45b0-96bd-603fb4255d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949318811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2949318811 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3503016143 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 531257164 ps |
| CPU time | 2.32 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:37 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-077db111-9a03-419a-8b1f-75f82d5dc0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503016143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3503016143 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.905360944 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 115069253 ps |
| CPU time | 0.85 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:17 PM PDT 24 |
| Peak memory | 204436 kb |
| Host | smart-cc903767-bb3a-4443-8c29-f9a13b72335f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905360944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.905360944 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.4221878468 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 52416779 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-351a7809-0075-412d-b66d-c1f89987c843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221878468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4221878468 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3941918516 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 19670969 ps |
| CPU time | 0.78 seconds |
| Started | Aug 19 04:25:14 PM PDT 24 |
| Finished | Aug 19 04:25:15 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-71b8cd74-afd9-4b1d-999f-826301ffbb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941918516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3941918516 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2557967283 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 120056435 ps |
| CPU time | 2.11 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:30 PM PDT 24 |
| Peak memory | 204676 kb |
| Host | smart-33e0441e-5acf-442b-8126-d5e0a93ad93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557967283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2557967283 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1961000203 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 142729489 ps |
| CPU time | 2.07 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:23 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-5ae40584-f6c2-4519-aef4-a2ace3b27b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961000203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1961000203 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2854674881 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 321076842 ps |
| CPU time | 1.5 seconds |
| Started | Aug 19 04:25:29 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-13f652f2-abae-4040-a9ba-99afdae828b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854674881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2854674881 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1642253927 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 143350027 ps |
| CPU time | 2.16 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-0ccd0384-292f-4b64-97c8-382da611cb83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642253927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1642253927 |
| Directory | /workspace/3.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.906104134 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 29252461 ps |
| CPU time | 1.19 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-0ccfeb9a-e916-4ccc-ad2e-1f65fd9b95d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906104134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.906104134 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3972517416 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 224690770 ps |
| CPU time | 2.6 seconds |
| Started | Aug 19 04:25:20 PM PDT 24 |
| Finished | Aug 19 04:25:23 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-beaba4fe-1733-45ff-a1f0-9412c2314ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972517416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3972517416 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4052940461 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 22130834 ps |
| CPU time | 0.79 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:17 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-0bc917aa-70c0-41aa-87e8-edfefe0e85fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052940461 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4052940461 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2462723013 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17065993 ps |
| CPU time | 0.77 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-2208e642-328b-4270-ab36-98a7219642cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462723013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2462723013 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3472892318 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 625810711 ps |
| CPU time | 2.1 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-bae367f2-33f6-4403-ba0b-3718ec926779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472892318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3472892318 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3228030593 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 927308135 ps |
| CPU time | 2.92 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-65403600-9086-496c-b988-86ed9e94aa12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228030593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3228030593 |
| Directory | /workspace/1.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.837198380 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 37635682 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204332 kb |
| Host | smart-a42825fa-f59e-4803-a8d6-eac30f0112a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837198380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.837198380 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.260906451 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 24757276 ps |
| CPU time | 1.19 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-acdaf412-ccc5-4a3d-aed5-857b1599ce4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260906451 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.260906451 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1199461069 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 167864856 ps |
| CPU time | 0.76 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:17 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-97fd08f9-738c-43a6-a80d-050f1ac9f829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199461069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1199461069 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.1370892858 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 44462505 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:15 PM PDT 24 |
| Finished | Aug 19 04:25:16 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-3a8cd714-2ce5-411d-a4df-a9d7f392882d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370892858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1370892858 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2829787473 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 69130592 ps |
| CPU time | 0.84 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:17 PM PDT 24 |
| Peak memory | 204460 kb |
| Host | smart-2ac9a113-f4d2-4630-b82f-1c274701b895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829787473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.2829787473 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1912030162 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 451793218 ps |
| CPU time | 2.13 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204740 kb |
| Host | smart-50512754-da8e-4394-998c-527d52abd9bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912030162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1912030162 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.761082739 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 319229153 ps |
| CPU time | 1.47 seconds |
| Started | Aug 19 04:25:22 PM PDT 24 |
| Finished | Aug 19 04:25:24 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-cb6c3f8c-88ce-467b-a9c6-ed6ac4b9756a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761082739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.761082739 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3220282720 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 346128653 ps |
| CPU time | 0.94 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:30 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-2ffe778a-63fd-4b19-806b-7fa96374e143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220282720 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3220282720 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1383832505 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 56899984 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:33 PM PDT 24 |
| Finished | Aug 19 04:25:34 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-f4a0ff06-0422-4b0c-9c0c-0b389486f6a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383832505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1383832505 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.3411814389 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 17425970 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:33 PM PDT 24 |
| Finished | Aug 19 04:25:34 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-2f8d75a6-4ee6-4bd6-a723-956d14f1f658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411814389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3411814389 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2306188416 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 42861569 ps |
| CPU time | 0.87 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:27 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-bda582ab-8d48-4546-9bf7-858bdcfa5668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306188416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.2306188416 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2573907128 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 53135247 ps |
| CPU time | 1.44 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:27 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-e9e33917-47c9-4ccd-94d8-b302e574784e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573907128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2573907128 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1736011707 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 80012876 ps |
| CPU time | 0.78 seconds |
| Started | Aug 19 04:25:31 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-4ab716e5-b11d-4cd2-9c99-ecee421bf914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736011707 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1736011707 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2652775446 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 23808188 ps |
| CPU time | 0.74 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:27 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-6561452a-dc5d-4f91-bc9f-0b2bf74a1cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652775446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2652775446 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3672090708 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 18995185 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:49 PM PDT 24 |
| Finished | Aug 19 04:25:50 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-c2e32dc3-028b-49e3-918f-1d440a82154d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672090708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3672090708 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.66114146 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 42244548 ps |
| CPU time | 0.95 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-1c66fce9-5966-4dc2-b5fb-09115c3419fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66114146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_out standing.66114146 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1180336125 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 437900588 ps |
| CPU time | 2.38 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-f588681a-ccd6-4aba-b613-a92ed83ce2af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180336125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1180336125 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.718544292 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 60928339 ps |
| CPU time | 1.51 seconds |
| Started | Aug 19 04:25:38 PM PDT 24 |
| Finished | Aug 19 04:25:40 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-ce6b54eb-f990-43fa-8ce6-86df0fabcb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718544292 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.718544292 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2242434718 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 21748937 ps |
| CPU time | 0.75 seconds |
| Started | Aug 19 04:25:45 PM PDT 24 |
| Finished | Aug 19 04:25:46 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-bf7547b1-53fe-40d3-8e81-83dc314d9907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242434718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2242434718 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.1760233567 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 19694438 ps |
| CPU time | 0.7 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-5eed9ec4-f536-4646-908c-dfa54cfb031e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760233567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1760233567 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3081406506 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 127064591 ps |
| CPU time | 0.96 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-7cf941bf-2089-4ab6-949a-f20b1b8fdfd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081406506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.3081406506 |
| Directory | /workspace/12.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3490310125 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 246671140 ps |
| CPU time | 1.56 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204700 kb |
| Host | smart-f6ec3df8-15a8-4354-b79f-89188493e92f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490310125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3490310125 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2482646832 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 123066412 ps |
| CPU time | 2.35 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:37 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-9b5ce4a3-08cd-4497-a60c-405f87cc44ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482646832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2482646832 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.157114196 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 27404736 ps |
| CPU time | 0.83 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-ed8ccc6a-84d5-41cc-ba36-3aee6bbe96cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157114196 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.157114196 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1443401894 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 29070116 ps |
| CPU time | 0.83 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204196 kb |
| Host | smart-9c204c35-0767-4892-b90b-10c63939de58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443401894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1443401894 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.421071619 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 18762213 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:25 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-050e0932-414a-4642-a714-2f02d467dd87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421071619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.421071619 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.520199584 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 166361594 ps |
| CPU time | 1.08 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-fac6f36b-b40e-440a-aeca-ccb661da6b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520199584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou tstanding.520199584 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1283778828 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 61405686 ps |
| CPU time | 1.48 seconds |
| Started | Aug 19 04:25:34 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204672 kb |
| Host | smart-95ac517f-0e90-4eb7-aeac-954624247649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283778828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1283778828 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1892349781 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 517457788 ps |
| CPU time | 2.07 seconds |
| Started | Aug 19 04:25:24 PM PDT 24 |
| Finished | Aug 19 04:25:26 PM PDT 24 |
| Peak memory | 204700 kb |
| Host | smart-82b2ad00-d748-462c-ad9f-5de29c7ed7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892349781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1892349781 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3797192580 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 25749821 ps |
| CPU time | 0.79 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204064 kb |
| Host | smart-7847e387-1679-40c7-a0ed-ee022a41b6bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797192580 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3797192580 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2259507457 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 31585886 ps |
| CPU time | 0.7 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:29 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-2e5f93e2-a961-49c8-8b5d-6fdbd168a71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259507457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2259507457 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.586615710 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 18316598 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:26 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-a4ba5764-2d07-4760-b9e9-01e8d63e9bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586615710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.586615710 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.62536444 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 61560379 ps |
| CPU time | 0.84 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 203932 kb |
| Host | smart-99047ae3-5ee1-4073-93f1-6e8a323b0f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62536444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_out standing.62536444 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2111217559 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 127604413 ps |
| CPU time | 1.09 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-418f1e1e-e803-4a34-be08-e7a55906f47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111217559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2111217559 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1749225730 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 286596924 ps |
| CPU time | 1.91 seconds |
| Started | Aug 19 04:25:33 PM PDT 24 |
| Finished | Aug 19 04:25:35 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-aa24b383-744f-4132-be74-dddb7c0218be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749225730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1749225730 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3834299576 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 23365293 ps |
| CPU time | 0.84 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-b65e1b7a-866f-45e7-bb79-3ee8e90980eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834299576 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3834299576 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.387613555 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 29447176 ps |
| CPU time | 0.81 seconds |
| Started | Aug 19 04:25:29 PM PDT 24 |
| Finished | Aug 19 04:25:30 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-468cf4bf-bcc7-4e6a-81d0-f522d4b7f646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387613555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.387613555 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.4105973870 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25701129 ps |
| CPU time | 0.64 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-2c1f0b95-ad81-4bf7-a615-35c9dacb36fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105973870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.4105973870 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1476321621 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 140545565 ps |
| CPU time | 1.17 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204420 kb |
| Host | smart-9db0e418-a3a7-403c-9677-13053e4e7d4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476321621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1476321621 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.911415082 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 137742001 ps |
| CPU time | 2.64 seconds |
| Started | Aug 19 04:25:31 PM PDT 24 |
| Finished | Aug 19 04:25:34 PM PDT 24 |
| Peak memory | 204736 kb |
| Host | smart-4dba112d-2a02-4e4b-9713-ff835877c66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911415082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.911415082 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.933492833 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 43811149 ps |
| CPU time | 1.36 seconds |
| Started | Aug 19 04:25:31 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-1c8bd2f3-a940-4cf9-aaca-f535f63c1bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933492833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.933492833 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3665550522 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 39731859 ps |
| CPU time | 1.12 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204704 kb |
| Host | smart-26e37c5d-a859-4019-a982-d497600ccf8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665550522 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3665550522 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3896580275 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 28796533 ps |
| CPU time | 0.82 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-9bb43c72-4684-40ba-bce9-264027b8bf48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896580275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3896580275 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.2302296717 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 122548848 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-dfa68639-0a6a-4d5c-8590-d447a192128e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302296717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2302296717 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1223226954 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 133986782 ps |
| CPU time | 1.29 seconds |
| Started | Aug 19 04:25:44 PM PDT 24 |
| Finished | Aug 19 04:25:46 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-9d5759cd-aac1-4938-8a7a-10e6f83cac05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223226954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.1223226954 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.344479290 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 464589043 ps |
| CPU time | 1.72 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-f19cc9c8-aa42-4105-8308-48b175400497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344479290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.344479290 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.977035149 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 549741682 ps |
| CPU time | 2.34 seconds |
| Started | Aug 19 04:25:42 PM PDT 24 |
| Finished | Aug 19 04:25:45 PM PDT 24 |
| Peak memory | 204680 kb |
| Host | smart-52835a5c-a2ae-4659-b841-226331e2057d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977035149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.977035149 |
| Directory | /workspace/16.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.618983940 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 112674496 ps |
| CPU time | 1.28 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204760 kb |
| Host | smart-22696096-c658-4bbf-92bc-aacead83b52a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618983940 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.618983940 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2421920402 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 35039287 ps |
| CPU time | 0.78 seconds |
| Started | Aug 19 04:25:42 PM PDT 24 |
| Finished | Aug 19 04:25:43 PM PDT 24 |
| Peak memory | 204400 kb |
| Host | smart-8a1e0e94-b0ee-4cc5-8e62-7b8c25250952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421920402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2421920402 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.2801942632 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 38361301 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:45 PM PDT 24 |
| Finished | Aug 19 04:25:45 PM PDT 24 |
| Peak memory | 204352 kb |
| Host | smart-9995fbc4-e4a0-410b-b3a1-73dc097f2d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801942632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2801942632 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.924696371 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 109362840 ps |
| CPU time | 1.11 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-75442875-7b1e-41c1-b1ad-c8877e08618f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924696371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou tstanding.924696371 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1098915734 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 219482839 ps |
| CPU time | 1.54 seconds |
| Started | Aug 19 04:25:54 PM PDT 24 |
| Finished | Aug 19 04:25:55 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-f3ba2826-37e5-4798-8539-79444287aa00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098915734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1098915734 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1149166038 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 24588919 ps |
| CPU time | 0.95 seconds |
| Started | Aug 19 04:25:29 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-078e389a-2687-4cb3-a1ee-d3260cdb9d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149166038 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1149166038 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1798896825 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 54104231 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:40 PM PDT 24 |
| Finished | Aug 19 04:25:41 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-999cfbdf-ca03-4eb1-97fe-085ee40d1b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798896825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1798896825 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2764497258 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 51869399 ps |
| CPU time | 1.16 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:29 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-367a9749-b895-40df-ba84-05ea927c08cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764497258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2764497258 |
| Directory | /workspace/18.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.224986750 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 157838499 ps |
| CPU time | 2.45 seconds |
| Started | Aug 19 04:25:44 PM PDT 24 |
| Finished | Aug 19 04:25:47 PM PDT 24 |
| Peak memory | 204732 kb |
| Host | smart-00f0c540-7f35-49eb-8d76-70dc13687c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224986750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.224986750 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2140394247 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 72336218 ps |
| CPU time | 1.49 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-1643bd83-bf4b-4049-b72c-2cbb66ce129d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140394247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2140394247 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1825028778 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 65807292 ps |
| CPU time | 1.05 seconds |
| Started | Aug 19 04:25:56 PM PDT 24 |
| Finished | Aug 19 04:25:58 PM PDT 24 |
| Peak memory | 204736 kb |
| Host | smart-12bd3c51-4da3-4e64-a0a8-b07614b938fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825028778 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1825028778 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2327086959 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 81374387 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:39 PM PDT 24 |
| Finished | Aug 19 04:25:40 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-7cb82934-63d4-4001-a696-3ee92427282c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327086959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2327086959 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.2781071117 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 20812045 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:48 PM PDT 24 |
| Finished | Aug 19 04:25:49 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-173b5a46-304c-491b-9549-fa0d5418c868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781071117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2781071117 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1024205241 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 223002123 ps |
| CPU time | 0.82 seconds |
| Started | Aug 19 04:25:25 PM PDT 24 |
| Finished | Aug 19 04:25:26 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-485ca0a4-82c2-426c-b11e-5d950f064d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024205241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1024205241 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.283985657 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 56688683 ps |
| CPU time | 1.36 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-8f1d8eb9-e317-4352-82af-fed1e61c1db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283985657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.283985657 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1220261460 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 258419460 ps |
| CPU time | 1.44 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:29 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-9c0e5db9-fb90-4ba1-9a5f-940e91008e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220261460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1220261460 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2663580412 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 38546245 ps |
| CPU time | 1.76 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-a72ba364-93d2-47ea-8e77-4f787780c1ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663580412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2663580412 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2671771699 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1182292427 ps |
| CPU time | 2.81 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-d4bd8629-3178-4d8a-9219-87c264118e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671771699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2671771699 |
| Directory | /workspace/2.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1859232316 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 34947604 ps |
| CPU time | 0.92 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:20 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-c7944b8c-8d7e-4120-b7bc-bb01174780fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859232316 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1859232316 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3926360997 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 19780055 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204168 kb |
| Host | smart-9e00db91-100f-48b7-b66a-699f56df1f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926360997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3926360997 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.3701560210 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 34562395 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:17 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-be08ae2d-65b9-48bd-a802-044384a3f21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701560210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3701560210 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3989393649 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 62824835 ps |
| CPU time | 0.92 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204676 kb |
| Host | smart-e7209d8c-0171-411f-84ef-e8d71aa8f6e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989393649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.3989393649 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.684975347 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 151543923 ps |
| CPU time | 2.06 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-0e510e59-bb44-4868-9636-637720da105a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684975347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.684975347 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2271024723 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 229967630 ps |
| CPU time | 1.34 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-089c3ea9-6281-4a67-9767-cef880e6bc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271024723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2271024723 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.3592192292 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 19690910 ps |
| CPU time | 0.7 seconds |
| Started | Aug 19 04:25:37 PM PDT 24 |
| Finished | Aug 19 04:25:38 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-3731e207-c700-4c1e-9b13-a5982e937dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592192292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3592192292 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.1662837624 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 32554922 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:39 PM PDT 24 |
| Finished | Aug 19 04:25:40 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-72e3b061-31d5-411d-9e0f-d2b3a8633c34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662837624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1662837624 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.4024273772 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 15944807 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:56 PM PDT 24 |
| Finished | Aug 19 04:25:57 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-dfbd4610-f9e8-47ec-93f9-da6385978f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024273772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4024273772 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.801419948 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 38330315 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:48 PM PDT 24 |
| Finished | Aug 19 04:25:49 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-09d6b3e8-ff35-4de1-b69e-7f0d26954f79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801419948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.801419948 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.1980500743 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 38871689 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:51 PM PDT 24 |
| Finished | Aug 19 04:25:52 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-bc11b991-7fde-4df6-aa8d-efe44e79dc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980500743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1980500743 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.1635037462 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 37750221 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:55 PM PDT 24 |
| Finished | Aug 19 04:25:56 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-9996c486-1ccd-42ba-8ef4-c2ebbaa1c17f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635037462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1635037462 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.3402362712 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 18561140 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:41 PM PDT 24 |
| Finished | Aug 19 04:25:42 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-b5241809-4790-4f82-8370-c14c4d621ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402362712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3402362712 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.4240842006 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 107741752 ps |
| CPU time | 0.73 seconds |
| Started | Aug 19 04:25:51 PM PDT 24 |
| Finished | Aug 19 04:25:52 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-f482f52e-f903-4c50-9931-facf4261f544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240842006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.4240842006 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1360555147 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 23165440 ps |
| CPU time | 0.64 seconds |
| Started | Aug 19 04:25:44 PM PDT 24 |
| Finished | Aug 19 04:25:44 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-864900f3-68bb-458e-a8c3-c69fe1e22bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360555147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1360555147 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3670831800 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 86415096 ps |
| CPU time | 1.23 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-82aba895-1e6d-47b5-9b73-aa4b3f905415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670831800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3670831800 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1457560710 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 226836232 ps |
| CPU time | 4.33 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-02923077-e285-42c0-b102-c58941bcc3ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457560710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1457560710 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2415258538 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 79030827 ps |
| CPU time | 0.73 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-8bb4532d-cb9e-4c00-a699-1453477c4c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415258538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2415258538 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1051652242 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 33625741 ps |
| CPU time | 1.48 seconds |
| Started | Aug 19 04:25:22 PM PDT 24 |
| Finished | Aug 19 04:25:23 PM PDT 24 |
| Peak memory | 212956 kb |
| Host | smart-f225c181-7a8b-4d37-8e04-fc0dcfd55fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051652242 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1051652242 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3219081549 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 27241386 ps |
| CPU time | 0.8 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-f7abb5cc-039a-4024-a99a-95b99aac9283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219081549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3219081549 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2695701158 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 85442347 ps |
| CPU time | 1.05 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-ecb08bdf-e428-4683-915b-5c415fabcbe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695701158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.2695701158 |
| Directory | /workspace/3.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2966076945 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 210738947 ps |
| CPU time | 1.27 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-5492d02b-ca70-4783-8b6c-a4558a583d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966076945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2966076945 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.1418149112 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 20759664 ps |
| CPU time | 0.61 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-e028f341-ccca-41d3-8bee-b06747dd102c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418149112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1418149112 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.364862684 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 15791257 ps |
| CPU time | 0.74 seconds |
| Started | Aug 19 04:25:36 PM PDT 24 |
| Finished | Aug 19 04:25:37 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-dba22f8d-1faa-4fe7-8609-99c7bdba0ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364862684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.364862684 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.2087246659 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 62503579 ps |
| CPU time | 0.72 seconds |
| Started | Aug 19 04:25:56 PM PDT 24 |
| Finished | Aug 19 04:25:57 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-55c56fcf-a9a3-4b2c-bcf3-a27eadc6fd3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087246659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2087246659 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.1215115365 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 53427835 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-552e12ca-d9e1-4527-a7c8-f8addebbee3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215115365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1215115365 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1665206141 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 45697123 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:59 PM PDT 24 |
| Finished | Aug 19 04:25:59 PM PDT 24 |
| Peak memory | 204436 kb |
| Host | smart-4d844feb-65c2-495c-b712-8826798e0433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665206141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1665206141 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.2164606401 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 58387940 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:44 PM PDT 24 |
| Finished | Aug 19 04:25:44 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-4b12a603-e73c-4226-b6a8-fd389538c440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164606401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2164606401 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.441470986 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 19946411 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:48 PM PDT 24 |
| Finished | Aug 19 04:25:49 PM PDT 24 |
| Peak memory | 204348 kb |
| Host | smart-a9069efc-c7b1-48d6-869d-ba8b3fbc59a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441470986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.441470986 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.847340343 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 54491273 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:56 PM PDT 24 |
| Finished | Aug 19 04:25:57 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-053b73d5-8894-4cb6-a80f-ef77dfb6b7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847340343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.847340343 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.257575688 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 143731691 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:36 PM PDT 24 |
| Finished | Aug 19 04:25:37 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-bf4746f2-481d-4c58-bee3-8d5aea3d0085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257575688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.257575688 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2405840885 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 33874169 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:51 PM PDT 24 |
| Finished | Aug 19 04:25:52 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-861c55ba-8dd7-4392-8378-267c1bf613a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405840885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2405840885 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2007325372 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 100698915 ps |
| CPU time | 1.21 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-bcf240fc-cd86-4bd1-a0ca-1f9826ef8bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007325372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2007325372 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1256304944 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1926872525 ps |
| CPU time | 5.11 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-691746bf-cb0d-4be7-a402-c256a3ff5783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256304944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1256304944 |
| Directory | /workspace/4.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.725819265 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 21883049 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:16 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-a79c3968-ae0a-432c-b2f9-0363173fc36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725819265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.725819265 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.725628590 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 55206692 ps |
| CPU time | 0.91 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-2880f01e-75d5-406b-a178-5687492c303c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725628590 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.725628590 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2439681471 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 22191034 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:22 PM PDT 24 |
| Finished | Aug 19 04:25:23 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-46cbab7f-09ef-42b3-9789-8e7fd2d37a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439681471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2439681471 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.1033946881 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 49349041 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-81306e74-343e-489d-822e-3dbe223ac9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033946881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1033946881 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1725094277 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 28993504 ps |
| CPU time | 1.13 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204672 kb |
| Host | smart-626014fd-0257-4670-aa2e-4ea03d97e9cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725094277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.1725094277 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4212155303 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 234698307 ps |
| CPU time | 1.36 seconds |
| Started | Aug 19 04:25:20 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-cc0eeabb-7aa6-47e6-8ff3-706cca1928e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212155303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4212155303 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.960611340 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 18189443 ps |
| CPU time | 0.7 seconds |
| Started | Aug 19 04:25:54 PM PDT 24 |
| Finished | Aug 19 04:25:55 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-c9c11031-ab79-4360-a184-e087713bb55e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960611340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.960611340 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.1898631936 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 47970597 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:48 PM PDT 24 |
| Finished | Aug 19 04:25:49 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-fa832cc8-ef77-4d93-a17b-3f60b2de2b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898631936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1898631936 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.2735900869 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 26760492 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:46 PM PDT 24 |
| Finished | Aug 19 04:25:47 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-6ea8f957-ab95-441d-9d31-e2f1e08745aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735900869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2735900869 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.1062332374 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 15511749 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:47 PM PDT 24 |
| Finished | Aug 19 04:25:47 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-1f43889b-542a-41e2-a618-90f32ba8e967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062332374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1062332374 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.1128938678 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 101891639 ps |
| CPU time | 0.64 seconds |
| Started | Aug 19 04:25:47 PM PDT 24 |
| Finished | Aug 19 04:25:48 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-4ef7c1d7-9444-4fc9-8db7-55f1122877a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128938678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1128938678 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2128107696 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 45630320 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:36 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-875ccf06-8679-409a-87ca-ddc7f348eb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128107696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2128107696 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.432680729 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 41265067 ps |
| CPU time | 0.64 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:36 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-9335f218-9cbd-4dee-8385-169abdc5e55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432680729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.432680729 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.344671240 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 35605510 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:42 PM PDT 24 |
| Finished | Aug 19 04:25:43 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-6a3807c9-a40c-4ce6-b1fd-a012e18b0082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344671240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.344671240 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.3218894403 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 55641637 ps |
| CPU time | 0.71 seconds |
| Started | Aug 19 04:25:36 PM PDT 24 |
| Finished | Aug 19 04:25:37 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-be7277f8-3121-45fc-b672-864f3789c73a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218894403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3218894403 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1448440039 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 27427243 ps |
| CPU time | 0.85 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-611fb4a5-02e1-4391-9ac6-053d957d5e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448440039 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1448440039 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3575271572 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25752962 ps |
| CPU time | 0.81 seconds |
| Started | Aug 19 04:25:17 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204400 kb |
| Host | smart-9aadabbe-7595-478c-8749-aea3f050556b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575271572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3575271572 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2798753027 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 19565513 ps |
| CPU time | 0.68 seconds |
| Started | Aug 19 04:25:24 PM PDT 24 |
| Finished | Aug 19 04:25:25 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-c1d5762b-dd66-473d-8ffe-0a8945d70c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798753027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2798753027 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.429158572 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 77315640 ps |
| CPU time | 1.13 seconds |
| Started | Aug 19 04:25:19 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-28455f4f-3565-4a69-b3ca-952496843f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429158572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out standing.429158572 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1145444347 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 257464745 ps |
| CPU time | 1.65 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:18 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-f090b9f8-70a6-412d-a9d8-04fcfdb4de6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145444347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1145444347 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2233245155 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 70117037 ps |
| CPU time | 1.51 seconds |
| Started | Aug 19 04:25:20 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-d6506969-52a7-452b-a4dc-b2286f765f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233245155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2233245155 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2919192547 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 39784530 ps |
| CPU time | 0.99 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:22 PM PDT 24 |
| Peak memory | 204352 kb |
| Host | smart-a3e02dc1-7daf-418a-b671-403a9862ce61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919192547 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2919192547 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3148733931 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 160567808 ps |
| CPU time | 0.75 seconds |
| Started | Aug 19 04:25:18 PM PDT 24 |
| Finished | Aug 19 04:25:24 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-234b59e5-a6d1-42af-a3bf-27f4829b74ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148733931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3148733931 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.3961217196 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 24976397 ps |
| CPU time | 0.64 seconds |
| Started | Aug 19 04:25:21 PM PDT 24 |
| Finished | Aug 19 04:25:21 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-b3a5ac20-531c-4c6d-b69f-f26c2481d106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961217196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3961217196 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4203321605 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 50744829 ps |
| CPU time | 2.44 seconds |
| Started | Aug 19 04:25:16 PM PDT 24 |
| Finished | Aug 19 04:25:19 PM PDT 24 |
| Peak memory | 212948 kb |
| Host | smart-115a678f-7639-45c0-b4da-ca877cef6b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203321605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4203321605 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4225660680 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 245623609 ps |
| CPU time | 1.34 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:30 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-47949ab4-e10e-4ef5-b446-916e33835e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225660680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4225660680 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2369655494 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 36455311 ps |
| CPU time | 1.52 seconds |
| Started | Aug 19 04:25:37 PM PDT 24 |
| Finished | Aug 19 04:25:39 PM PDT 24 |
| Peak memory | 204740 kb |
| Host | smart-94b36eab-a449-4836-aaa9-1c139433cb13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369655494 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2369655494 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2273152976 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 135136935 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:44 PM PDT 24 |
| Finished | Aug 19 04:25:44 PM PDT 24 |
| Peak memory | 204352 kb |
| Host | smart-24c6541b-38ce-4aac-8b4c-f7e2ade3cc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273152976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2273152976 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.3491316152 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 17946349 ps |
| CPU time | 0.69 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204456 kb |
| Host | smart-b20d4955-2901-4e4c-be6b-2db215d12e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491316152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3491316152 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.578815336 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 62775718 ps |
| CPU time | 1.55 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-c4e6d682-ea27-47c1-99c9-e529befaf8bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578815336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.578815336 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2277777137 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 127730154 ps |
| CPU time | 1.38 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-e1dd7520-f34f-472e-b8ac-f2f6cd1ba567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277777137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2277777137 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.437588546 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 89857689 ps |
| CPU time | 1.14 seconds |
| Started | Aug 19 04:25:27 PM PDT 24 |
| Finished | Aug 19 04:25:28 PM PDT 24 |
| Peak memory | 204768 kb |
| Host | smart-eba1042f-3540-4be9-8ef9-e18b33171d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437588546 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.437588546 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2964366829 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 103247184 ps |
| CPU time | 0.75 seconds |
| Started | Aug 19 04:25:32 PM PDT 24 |
| Finished | Aug 19 04:25:33 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-879f3dda-8b5c-421d-8c67-30de3c0154ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964366829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2964366829 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.305398492 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 55250077 ps |
| CPU time | 0.67 seconds |
| Started | Aug 19 04:25:34 PM PDT 24 |
| Finished | Aug 19 04:25:35 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-202801c3-28ac-4a73-95d3-b0154b223da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305398492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.305398492 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.535496111 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 64095973 ps |
| CPU time | 0.87 seconds |
| Started | Aug 19 04:25:31 PM PDT 24 |
| Finished | Aug 19 04:25:32 PM PDT 24 |
| Peak memory | 204460 kb |
| Host | smart-a4442b42-5f23-4f77-928e-48b501b8465a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535496111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out standing.535496111 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1373429207 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 57704725 ps |
| CPU time | 1.43 seconds |
| Started | Aug 19 04:25:37 PM PDT 24 |
| Finished | Aug 19 04:25:39 PM PDT 24 |
| Peak memory | 204704 kb |
| Host | smart-7b5f79f7-63e1-4ed9-a55e-49f6b0407b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373429207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1373429207 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1473395728 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 158144449 ps |
| CPU time | 2.18 seconds |
| Started | Aug 19 04:25:35 PM PDT 24 |
| Finished | Aug 19 04:25:38 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-f14d105c-3abc-4a28-94c1-bf6c02dc79de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473395728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1473395728 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3984555022 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 35422102 ps |
| CPU time | 0.91 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:29 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-bbf24c3b-ae36-4537-99be-378e4ceac76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984555022 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3984555022 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1226876234 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 51239539 ps |
| CPU time | 0.66 seconds |
| Started | Aug 19 04:25:34 PM PDT 24 |
| Finished | Aug 19 04:25:35 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-c69fc22d-734b-42fe-ac4a-332e78629c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226876234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1226876234 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1345560403 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 37070005 ps |
| CPU time | 0.65 seconds |
| Started | Aug 19 04:25:28 PM PDT 24 |
| Finished | Aug 19 04:25:29 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-7ced9ee8-28e6-4af2-bf49-ab678ff88d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345560403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1345560403 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4110430096 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 35518670 ps |
| CPU time | 0.98 seconds |
| Started | Aug 19 04:25:30 PM PDT 24 |
| Finished | Aug 19 04:25:31 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-e5713512-4a11-43bb-be16-a398f2cee00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110430096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.4110430096 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2044889574 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 153789801 ps |
| CPU time | 1.59 seconds |
| Started | Aug 19 04:25:54 PM PDT 24 |
| Finished | Aug 19 04:25:55 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-693d30aa-77ba-44d4-a0db-072b03e8a38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044889574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2044889574 |
| Directory | /workspace/9.i2c_tl_errors/latest |
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