Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353	1			T5	5		T7	5		T4	1
all_pins[1]	353	1			T5	5		T7	5		T4	1
all_pins[2]	353	1			T5	5		T7	5		T4	1
all_pins[3]	353	1			T5	5		T7	5		T4	1
all_pins[4]	353	1			T5	5		T7	5		T4	1
all_pins[5]	353	1			T5	5		T7	5		T4	1
all_pins[6]	353	1			T5	5		T7	5		T4	1
all_pins[7]	353	1			T5	5		T7	5		T4	1
all_pins[8]	353	1			T5	5		T7	5		T4	1
all_pins[9]	353	1			T5	5		T7	5		T4	1
all_pins[10]	353	1			T5	5		T7	5		T4	1
all_pins[11]	353	1			T5	5		T7	5		T4	1
all_pins[12]	353	1			T5	5		T7	5		T4	1
all_pins[13]	353	1			T5	5		T7	5		T4	1
all_pins[14]	353	1			T5	5		T7	5		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4359	1			T5	61		T7	53		T4	15
values[0x1]	936	1			T5	14		T7	22		T9	22
transitions[0x0=>0x1]	700	1			T5	11		T7	14		T9	19
transitions[0x1=>0x0]	712	1			T5	11		T7	14		T9	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	301	1			T5	4		T7	4		T4	1
all_pins[0]	values[0x1]	52	1			T5	1		T7	1		T9	1
all_pins[0]	transitions[0x0=>0x1]	36	1			T5	1		T7	1		T9	1
all_pins[0]	transitions[0x1=>0x0]	49	1			T5	1		T7	1		T8	4
all_pins[1]	values[0x0]	288	1			T5	4		T7	4		T4	1
all_pins[1]	values[0x1]	65	1			T5	1		T7	1		T8	4
all_pins[1]	transitions[0x0=>0x1]	47	1			T7	1		T8	3		T10	1
all_pins[1]	transitions[0x1=>0x0]	36	1			T7	1		T8	1		T10	2
all_pins[2]	values[0x0]	299	1			T5	4		T7	4		T4	1
all_pins[2]	values[0x1]	54	1			T5	1		T7	1		T8	2
all_pins[2]	transitions[0x0=>0x1]	42	1			T5	1		T7	1		T8	1
all_pins[2]	transitions[0x1=>0x0]	55	1			T9	3		T8	3		T58	1
all_pins[3]	values[0x0]	286	1			T5	5		T7	5		T4	1
all_pins[3]	values[0x1]	67	1			T9	3		T8	4		T59	1
all_pins[3]	transitions[0x0=>0x1]	56	1			T9	3		T8	3		T59	1
all_pins[3]	transitions[0x1=>0x0]	44	1			T5	1		T10	2		T60	1
all_pins[4]	values[0x0]	298	1			T5	4		T7	5		T4	1
all_pins[4]	values[0x1]	55	1			T5	1		T8	1		T10	2
all_pins[4]	transitions[0x0=>0x1]	47	1			T5	1		T10	1		T60	1
all_pins[4]	transitions[0x1=>0x0]	51	1			T5	1		T7	2		T9	1
all_pins[5]	values[0x0]	294	1			T5	4		T7	3		T4	1
all_pins[5]	values[0x1]	59	1			T5	1		T7	2		T9	1
all_pins[5]	transitions[0x0=>0x1]	34	1			T9	1		T8	1		T10	1
all_pins[5]	transitions[0x1=>0x0]	65	1			T5	1		T7	1		T9	5
all_pins[6]	values[0x0]	263	1			T5	3		T7	2		T4	1
all_pins[6]	values[0x1]	90	1			T5	2		T7	3		T9	5
all_pins[6]	transitions[0x0=>0x1]	62	1			T5	2		T7	3		T9	3
all_pins[6]	transitions[0x1=>0x0]	46	1			T7	1		T10	2		T60	1
all_pins[7]	values[0x0]	279	1			T5	5		T7	4		T4	1
all_pins[7]	values[0x1]	74	1			T7	1		T9	2		T8	2
all_pins[7]	transitions[0x0=>0x1]	55	1			T7	1		T9	1		T10	2
all_pins[7]	transitions[0x1=>0x0]	51	1			T7	2		T9	1		T8	1
all_pins[8]	values[0x0]	283	1			T5	5		T7	3		T4	1
all_pins[8]	values[0x1]	70	1			T7	2		T9	2		T8	3
all_pins[8]	transitions[0x0=>0x1]	55	1			T9	2		T8	2		T10	1
all_pins[8]	transitions[0x1=>0x0]	36	1			T9	3		T10	2		T60	2
all_pins[9]	values[0x0]	302	1			T5	5		T7	3		T4	1
all_pins[9]	values[0x1]	51	1			T7	2		T9	3		T8	1
all_pins[9]	transitions[0x0=>0x1]	42	1			T7	2		T9	3		T8	1
all_pins[9]	transitions[0x1=>0x0]	46	1			T5	3		T7	1		T9	2
all_pins[10]	values[0x0]	298	1			T5	2		T7	4		T4	1
all_pins[10]	values[0x1]	55	1			T5	3		T7	1		T9	2
all_pins[10]	transitions[0x0=>0x1]	39	1			T5	2		T9	2		T10	3
all_pins[10]	transitions[0x1=>0x0]	45	1			T7	2		T9	1		T8	2
all_pins[11]	values[0x0]	292	1			T5	4		T7	2		T4	1
all_pins[11]	values[0x1]	61	1			T5	1		T7	3		T9	1
all_pins[11]	transitions[0x0=>0x1]	50	1			T5	1		T7	2		T9	1
all_pins[11]	transitions[0x1=>0x0]	43	1			T5	2		T8	4		T10	1
all_pins[12]	values[0x0]	299	1			T5	3		T7	4		T4	1
all_pins[12]	values[0x1]	54	1			T5	2		T7	1		T8	5
all_pins[12]	transitions[0x0=>0x1]	43	1			T5	2		T8	5		T61	1
all_pins[12]	transitions[0x1=>0x0]	46	1			T5	1		T7	2		T9	1
all_pins[13]	values[0x0]	296	1			T5	4		T7	2		T4	1
all_pins[13]	values[0x1]	57	1			T5	1		T7	3		T9	1
all_pins[13]	transitions[0x0=>0x1]	48	1			T5	1		T7	3		T9	1
all_pins[13]	transitions[0x1=>0x0]	63	1			T7	1		T9	1		T8	1
all_pins[14]	values[0x0]	281	1			T5	5		T7	4		T4	1
all_pins[14]	values[0x1]	72	1			T7	1		T9	1		T8	1
all_pins[14]	transitions[0x0=>0x1]	44	1			T9	1		T61	2		T59	2
all_pins[14]	transitions[0x1=>0x0]	36	1			T5	1		T9	1		T8	1