Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T5	4		T7	4		T9	7
all_values[1]	284	1			T5	4		T7	4		T9	7
all_values[2]	284	1			T5	4		T7	4		T9	7
all_values[3]	284	1			T5	4		T7	4		T9	7
all_values[4]	284	1			T5	4		T7	4		T9	7
all_values[5]	284	1			T5	4		T7	4		T9	7
all_values[6]	284	1			T5	4		T7	4		T9	7
all_values[7]	284	1			T5	4		T7	4		T9	7
all_values[8]	284	1			T5	4		T7	4		T9	7
all_values[9]	284	1			T5	4		T7	4		T9	7
all_values[10]	284	1			T5	4		T7	4		T9	7
all_values[11]	284	1			T5	4		T7	4		T9	7
all_values[12]	284	1			T5	4		T7	4		T9	7
all_values[13]	284	1			T5	4		T7	4		T9	7
all_values[14]	284	1			T5	4		T7	4		T9	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2325

1

T5

40

T7

34

T9

56

auto[1]

1935

1

T5

20

T7

26

T9

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772

1

T5

9

T7

9

T9

15

auto[1]

3488

1

T5

51

T7

51

T9

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T5

33

T7

34

T9

64

auto[1]

1754

1

T5

27

T7

26

T9

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1			T8	1		T60	1		T59	1
all_values[0]	auto[0]	auto[0]	auto[1]	41	1			T7	2		T9	2		T10	1
all_values[0]	auto[0]	auto[1]	auto[0]	29	1			T9	1		T60	1		T61	2
all_values[0]	auto[0]	auto[1]	auto[1]	68	1			T5	1		T7	1		T9	1
all_values[0]	auto[1]	auto[0]	auto[1]	55	1			T5	3		T7	1		T9	1
all_values[0]	auto[1]	auto[1]	auto[1]	49	1			T9	2		T8	1		T10	1
all_values[1]	auto[0]	auto[0]	auto[0]	28	1			T7	2		T10	1		T61	2
all_values[1]	auto[0]	auto[0]	auto[1]	61	1			T5	1		T9	2		T10	3
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T61	3		T62	4		T63	1
all_values[1]	auto[0]	auto[1]	auto[1]	57	1			T5	1		T7	1		T9	2
all_values[1]	auto[1]	auto[0]	auto[1]	64	1			T5	1		T9	3		T8	1
all_values[1]	auto[1]	auto[1]	auto[1]	52	1			T5	1		T7	1		T8	3
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T5	1		T7	1		T8	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T5	1		T8	2		T10	1
all_values[2]	auto[0]	auto[1]	auto[0]	20	1			T9	2		T60	3		T61	1
all_values[2]	auto[0]	auto[1]	auto[1]	56	1			T5	1		T7	2		T9	4
all_values[2]	auto[1]	auto[0]	auto[1]	63	1			T9	1		T8	1		T10	2
all_values[2]	auto[1]	auto[1]	auto[1]	54	1			T5	1		T7	1		T8	2
all_values[3]	auto[0]	auto[0]	auto[0]	24	1			T9	1		T10	1		T61	4
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T7	2		T8	2		T10	2
all_values[3]	auto[0]	auto[1]	auto[0]	20	1			T61	3		T58	1		T64	3
all_values[3]	auto[0]	auto[1]	auto[1]	58	1			T5	2		T9	4		T8	1
all_values[3]	auto[1]	auto[0]	auto[1]	77	1			T5	1		T7	2		T9	2
all_values[3]	auto[1]	auto[1]	auto[1]	48	1			T5	1		T8	2		T10	1
all_values[4]	auto[0]	auto[0]	auto[0]	29	1			T5	1		T9	1		T10	2
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T7	2		T9	2		T8	2
all_values[4]	auto[0]	auto[1]	auto[0]	16	1			T9	2		T65	1		T64	1
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T5	1		T8	1		T60	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1			T5	2		T7	2		T9	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T10	1		T61	3		T59	1
all_values[5]	auto[0]	auto[0]	auto[0]	29	1			T8	1		T59	1		T58	2
all_values[5]	auto[0]	auto[0]	auto[1]	65	1			T5	1		T7	1		T9	4
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T58	2		T62	1		T66	1
all_values[5]	auto[0]	auto[1]	auto[1]	49	1			T5	1		T7	1		T8	1
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T5	2		T7	1		T9	2
all_values[5]	auto[1]	auto[1]	auto[1]	49	1			T7	1		T9	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T10	1		T60	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[1]	42	1			T5	1		T9	1		T61	3
all_values[6]	auto[0]	auto[1]	auto[0]	12	1			T58	2		T67	2		T63	2
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T7	2		T9	2		T8	3
all_values[6]	auto[1]	auto[0]	auto[1]	65	1			T5	1		T7	1		T8	2
all_values[6]	auto[1]	auto[1]	auto[1]	61	1			T5	2		T7	1		T9	4
all_values[7]	auto[0]	auto[0]	auto[0]	20	1			T7	1		T10	1		T59	2
all_values[7]	auto[0]	auto[0]	auto[1]	52	1			T5	2		T7	1		T9	2
all_values[7]	auto[0]	auto[1]	auto[0]	14	1			T68	3		T69	1		T70	1
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T8	2		T10	2		T60	2
all_values[7]	auto[1]	auto[0]	auto[1]	73	1			T5	2		T7	1		T9	5
all_values[7]	auto[1]	auto[1]	auto[1]	60	1			T7	1		T8	3		T10	1
all_values[8]	auto[0]	auto[0]	auto[0]	48	1			T5	3		T7	1		T8	1
all_values[8]	auto[0]	auto[0]	auto[1]	42	1			T9	2		T8	1		T60	1
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T5	1		T61	1		T58	2
all_values[8]	auto[0]	auto[1]	auto[1]	52	1			T7	1		T9	2		T8	1
all_values[8]	auto[1]	auto[0]	auto[1]	57	1			T7	1		T9	2		T10	3
all_values[8]	auto[1]	auto[1]	auto[1]	54	1			T7	1		T9	1		T8	4
all_values[9]	auto[0]	auto[0]	auto[0]	49	1			T7	1		T9	3		T61	3
all_values[9]	auto[0]	auto[0]	auto[1]	54	1			T5	2		T8	2		T10	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T59	3		T71	1		T68	1
all_values[9]	auto[0]	auto[1]	auto[1]	49	1			T7	1		T9	1		T8	2
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T5	2		T7	1		T8	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1			T7	1		T9	3		T8	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T9	1		T8	1		T60	3
all_values[10]	auto[0]	auto[0]	auto[1]	70	1			T7	1		T9	1		T8	1
all_values[10]	auto[0]	auto[1]	auto[0]	12	1			T60	1		T71	1		T68	1
all_values[10]	auto[0]	auto[1]	auto[1]	57	1			T5	1		T7	1		T9	2
all_values[10]	auto[1]	auto[0]	auto[1]	63	1			T5	1		T7	2		T9	2
all_values[10]	auto[1]	auto[1]	auto[1]	49	1			T5	2		T9	1		T8	1
all_values[11]	auto[0]	auto[0]	auto[0]	15	1			T67	2		T72	2		T73	2
all_values[11]	auto[0]	auto[0]	auto[1]	67	1			T5	3		T9	3		T8	1
all_values[11]	auto[0]	auto[1]	auto[0]	8	1			T58	1		T73	1		T74	2
all_values[11]	auto[0]	auto[1]	auto[1]	64	1			T7	1		T8	1		T10	1
all_values[11]	auto[1]	auto[0]	auto[1]	81	1			T5	1		T7	1		T9	2
all_values[11]	auto[1]	auto[1]	auto[1]	49	1			T7	2		T9	2		T61	3
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T5	1		T7	2		T9	1
all_values[12]	auto[0]	auto[0]	auto[1]	59	1			T9	2		T10	3		T60	1
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T68	1		T66	1		T70	1
all_values[12]	auto[0]	auto[1]	auto[1]	51	1			T5	1		T7	1		T9	2
all_values[12]	auto[1]	auto[0]	auto[1]	59	1			T9	2		T10	2		T60	1
all_values[12]	auto[1]	auto[1]	auto[1]	53	1			T5	2		T7	1		T8	5
all_values[13]	auto[0]	auto[0]	auto[0]	31	1			T9	3		T8	1		T60	1
all_values[13]	auto[0]	auto[0]	auto[1]	63	1			T5	2		T8	2		T10	1
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T59	1		T75	1		T67	2
all_values[13]	auto[0]	auto[1]	auto[1]	56	1			T5	1		T7	2		T9	3
all_values[13]	auto[1]	auto[0]	auto[1]	61	1			T5	1		T7	1		T8	4
all_values[13]	auto[1]	auto[1]	auto[1]	49	1			T7	1		T9	1		T10	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T5	2		T7	1		T8	1
all_values[14]	auto[0]	auto[0]	auto[1]	60	1			T5	1		T7	2		T9	1
all_values[14]	auto[0]	auto[1]	auto[0]	10	1			T60	1		T61	1		T75	3
all_values[14]	auto[0]	auto[1]	auto[1]	65	1			T9	4		T10	1		T61	1
all_values[14]	auto[1]	auto[0]	auto[1]	64	1			T5	1		T8	3		T10	3
all_values[14]	auto[1]	auto[1]	auto[1]	50	1			T7	1		T9	2		T8	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal