Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.48	100.00	100.00	93.91			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	97.30	89.84	97.22	72.62	94.40	98.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	87.98	96.36	84.40		72.62	91.82	94.69
i2c_csr_assert	93.75						93.75
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	98.67	98.59	97.16	100.00		97.58	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00

68                      
69         1/1            assign alert_test = {
           Tests:       T1 T2 T3 
70                          reg2hw.alert_test.q &
71                          reg2hw.alert_test.qe
72                        };
73                      
74                        for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
75                          prim_alert_sender #(
76                            .AsyncOn(AlertAsyncOn[i]),
77                            .IsFatal(1'b1)
78                          ) u_prim_alert_sender (
79                            .clk_i,
80                            .rst_ni,
81                            .alert_test_i  ( alert_test[i] ),
82                            .alert_req_i   ( alerts[0]     ),
83                            .alert_ack_o   (               ),
84                            .alert_state_o (               ),
85                            .alert_rx_i    ( alert_rx_i[i] ),
86                            .alert_tx_o    ( alert_tx_o[i] )
87                          );
88                        end
89                      
90                        logic scl_int;
91                        logic sda_int;
92                      
93                        i2c_core #(
94                          .InputDelayCycles(InputDelayCycles)
95                        ) i2c_core (
96                          .clk_i,
97                          .rst_ni,
98                          .ram_cfg_i,
99                      
100                         .reg2hw,
101                         .hw2reg,
102                     
103                         .scl_i(cio_scl_i),
104                         .scl_o(scl_int),
105                         .sda_i(cio_sda_i),
106                         .sda_o(sda_int),
107                     
108                         .intr_fmt_threshold_o,
109                         .intr_rx_threshold_o,
110                         .intr_acq_threshold_o,
111                         .intr_rx_overflow_o,
112                         .intr_controller_halt_o,
113                         .intr_scl_interference_o,
114                         .intr_sda_interference_o,
115                         .intr_stretch_timeout_o,
116                         .intr_sda_unstable_o,
117                         .intr_cmd_complete_o,
118                         .intr_tx_stretch_o,
119                         .intr_tx_threshold_o,
120                         .intr_acq_stretch_o,
121                         .intr_unexp_stop_o,
122                         .intr_host_timeout_o
123                       );
124                     
125                       // For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
126                       // Asserting scl or sda high should be equivalent to a tri-state output.
127                       // The output, when enabled, should only assert low.
128                     
129                       assign cio_scl_o = 1'b0;
130                       assign cio_sda_o = 1'b0;
131                     
132        1/1            assign cio_scl_en_o = ~scl_int;
           Tests:       T1 T2 T3 
133        1/1            assign cio_sda_en_o = ~sda_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T102,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	51	45	88.24
Total Bits	394	370	93.91
Total Bits 0->1	197	185	93.91
Total Bits 1->0	197	185	93.91

Ports	51	45	88.24
Port Bits	394	370	93.91
Port Bits 0->1	197	185	93.91
Port Bits 1->0	197	185	93.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T204,T17	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T205,T206,T207	Yes	T205,T206,T207	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T204,T208	Yes	T102,T204,T208	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T204,T208	Yes	T102,T204,T208	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T3,T68,T19	Yes	T3,T4,T5	OUTPUT
intr_rx_threshold_o	Yes	Yes	T10,T40,T41	Yes	T10,T40,T41	OUTPUT
intr_acq_threshold_o	Yes	Yes	T5,T9,T55	Yes	T5,T9,T55	OUTPUT
intr_rx_overflow_o	Yes	Yes	T86,T106,T107	Yes	T86,T106,T107	OUTPUT
intr_controller_halt_o	Yes	Yes	T3,T17,T11	Yes	T3,T17,T11	OUTPUT
intr_scl_interference_o	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
intr_sda_interference_o	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T3,T7,T10	Yes	T3,T7,T10	OUTPUT
intr_sda_unstable_o	Yes	Yes	T17,T18,T22	Yes	T17,T18,T22	OUTPUT
intr_cmd_complete_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_tx_stretch_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
intr_tx_threshold_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_acq_stretch_o	Yes	Yes	T4,T5,T51	Yes	T4,T5,T51	OUTPUT
intr_unexp_stop_o	Yes	Yes	T55,T57,T119	Yes	T55,T57,T119	OUTPUT
intr_host_timeout_o	Yes	Yes	T4,T81,T82	Yes	T4,T81,T82	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	408961761	408787796	0	0
CioSclEnKnownO_A	408961761	408787796	0	0
CioSclKnownO_A	408961761	408787796	0	0
CioSdaEnKnownO_A	408961761	408787796	0	0
CioSdaKnownO_A	408961761	408787796	0	0
FpvSecCmRegWeOnehotCheck_A	408961761	70	0	0
IntrAcqStretchKnownO_A	408961761	408787796	0	0
IntrAcqWtmkKnownO_A	408961761	408787796	0	0
IntrCommandCompleteKnownO_A	408961761	408787796	0	0
IntrControllerHaltKnownO_A	408961761	408787796	0	0
IntrFmtWtmkKnownO_A	408961761	408787796	0	0
IntrHostTimeoutKnownO_A	408961761	408787796	0	0
IntrRxOflwKnownO_A	408961761	408787796	0	0
IntrRxWtmkKnownO_A	408961761	408787796	0	0
IntrSclInterfKnownO_A	408961761	408787796	0	0
IntrSdaInterfKnownO_A	408961761	408787796	0	0
IntrSdaUnstableKnownO_A	408961761	408787796	0	0
IntrStretchTimeoutKnownO_A	408961761	408787796	0	0
IntrTxStretchKnownO_A	408961761	408787796	0	0
IntrTxWtmkKnownO_A	408961761	408787796	0	0
IntrUnexpStopKnownO_A	408961761	408787796	0	0
TlAReadyKnownO_A	408961761	408787796	0	0
TlDValidKnownO_A	408961761	408787796	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	70	0	0
T17	6139	0	0	0
T19	213495	0	0	0
T30	11728	0	0	0
T55	187705	0	0	0
T68	45068	0	0	0
T69	42850	0	0	0
T81	105995	0	0	0
T131	0	20	0	0
T167	129424	0	0	0
T169	0	10	0	0
T204	6023	20	0	0
T208	0	10	0	0
T209	0	10	0	0
T210	42796	0	0	0

IntrAcqStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrAcqWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrControllerHaltKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrTxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0