Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	409652789	0	0	0
ctrl_rd_A	409652789	2410	0	0
host_fifo_config_rd_A	409652789	5082	0	0
host_nack_handler_timeout_rd_A	409652789	1563	0	0
host_timeout_ctrl_rd_A	409652789	1377	0	0
intr_enable_rd_A	409652789	4414	0	0
ovrd_rd_A	409652789	2479	0	0
target_fifo_config_rd_A	409652789	1629	0	0
target_id_rd_A	409652789	1723	0	0
target_timeout_ctrl_rd_A	409652789	1723	0	0
timeout_ctrl_rd_A	409652789	1797	0	0
timing0_rd_A	409652789	1668	0	0
timing1_rd_A	409652789	1559	0	0
timing2_rd_A	409652789	1402	0	0
timing3_rd_A	409652789	1530	0	0
timing4_rd_A	409652789	1510	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	2410	0	0
T108	5544	77	0	0
T109	9953	50	0	0
T110	1955	2	0	0
T111	1938	11	0	0
T112	52257	391	0	0
T113	3341	18	0	0
T114	6282	19	0	0
T115	1919	29	0	0
T116	12335	231	0	0
T117	18331	97	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	5082	0	0
T42	279185	127	0	0
T87	0	144	0	0
T118	0	112	0	0
T119	0	414	0	0
T120	0	260	0	0
T121	0	211	0	0
T122	0	181	0	0
T123	0	120	0	0
T124	0	225	0	0
T125	0	75	0	0
T126	21079	0	0	0
T127	85206	0	0	0
T128	62469	0	0	0
T129	42513	0	0	0
T130	831	0	0	0
T131	10447	0	0	0
T132	15101	0	0	0
T133	167525	0	0	0
T134	136339	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1563	0	0
T108	5544	14	0	0
T109	9953	66	0	0
T110	1955	5	0	0
T111	1938	13	0	0
T112	52257	466	0	0
T113	3341	45	0	0
T114	6282	30	0	0
T115	1919	7	0	0
T116	12335	223	0	0
T135	2034	2	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1377	0	0
T108	5544	34	0	0
T109	9953	42	0	0
T110	1955	2	0	0
T111	1938	15	0	0
T112	52257	413	0	0
T113	3341	31	0	0
T114	6282	16	0	0
T115	1919	2	0	0
T116	12335	240	0	0
T135	2034	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	4414	0	0
T108	0	21	0	0
T109	0	2	0	0
T110	0	7	0	0
T111	0	14	0	0
T112	0	389	0	0
T119	113745	22	0	0
T136	0	16	0	0
T137	0	12	0	0
T138	0	12	0	0
T139	0	16	0	0
T140	34789	0	0	0
T141	7628	0	0	0
T142	53583	0	0	0
T143	51561	0	0	0
T144	185459	0	0	0
T145	57350	0	0	0
T146	9358	0	0	0
T147	59445	0	0	0
T148	49085	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	2479	0	0
T41	109345	0	0	0
T44	10885	0	0	0
T56	455543	0	0	0
T70	44861	0	0	0
T72	97061	0	0	0
T73	38800	0	0	0
T76	6337	0	0	0
T82	102045	0	0	0
T85	2346	38	0	0
T149	0	37	0	0
T150	0	34	0	0
T151	0	41	0	0
T152	0	26	0	0
T153	0	39	0	0
T154	0	19	0	0
T155	0	71	0	0
T156	0	60	0	0
T157	0	55	0	0
T158	125141	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1629	0	0
T108	5544	67	0	0
T109	9953	30	0	0
T110	1955	1	0	0
T111	1938	15	0	0
T112	52257	454	0	0
T113	3341	7	0	0
T114	6282	51	0	0
T115	1919	8	0	0
T135	2034	8	0	0
T159	1409	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1723	0	0
T108	5544	26	0	0
T109	9953	32	0	0
T110	1955	5	0	0
T111	1938	3	0	0
T112	52257	436	0	0
T113	3341	33	0	0
T114	6282	29	0	0
T115	1919	10	0	0
T135	2034	3	0	0
T159	1409	10	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1723	0	0
T108	5544	45	0	0
T109	9953	28	0	0
T110	1955	9	0	0
T111	1938	14	0	0
T112	52257	451	0	0
T113	3341	29	0	0
T114	6282	70	0	0
T115	1919	1	0	0
T116	12335	259	0	0
T135	2034	8	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1797	0	0
T108	5544	38	0	0
T109	9953	24	0	0
T110	1955	1	0	0
T111	1938	14	0	0
T112	52257	486	0	0
T113	3341	18	0	0
T114	6282	67	0	0
T115	1919	5	0	0
T135	2034	9	0	0
T159	1409	5	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1668	0	0
T108	5544	14	0	0
T109	9953	28	0	0
T110	1955	5	0	0
T112	52257	454	0	0
T113	3341	55	0	0
T114	6282	4	0	0
T115	1919	7	0	0
T116	12335	211	0	0
T135	2034	6	0	0
T159	1409	6	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1559	0	0
T108	5544	53	0	0
T109	9953	24	0	0
T110	1955	3	0	0
T111	1938	12	0	0
T112	52257	459	0	0
T113	3341	24	0	0
T114	6282	40	0	0
T115	1919	9	0	0
T116	12335	241	0	0
T135	2034	4	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1402	0	0
T108	5544	39	0	0
T109	9953	11	0	0
T110	1955	4	0	0
T111	1938	9	0	0
T112	52257	423	0	0
T113	3341	47	0	0
T114	6282	13	0	0
T115	1919	10	0	0
T116	12335	204	0	0
T135	2034	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1530	0	0
T108	5544	46	0	0
T109	9953	28	0	0
T110	1955	4	0	0
T111	1938	2	0	0
T112	52257	395	0	0
T113	3341	5	0	0
T114	6282	37	0	0
T115	1919	8	0	0
T135	2034	16	0	0
T159	1409	2	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409652789	1510	0	0
T108	5544	45	0	0
T109	9953	25	0	0
T110	1955	5	0	0
T111	1938	7	0	0
T112	52257	452	0	0
T113	3341	4	0	0
T114	6282	28	0	0
T115	1919	13	0	0
T116	12335	209	0	0
T159	1409	5	0	0