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Module Instance : tb.dut.u_reg.u_fdata_start

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fdata_stop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fdata_readb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fdata_rcont

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fdata_nakok

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fifo_ctrl_fmtrst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fifo_ctrl_acqrst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_fifo_ctrl_txrst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_host_fifo_config_rx_thresh

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_host_fifo_config_fmt_thresh

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_target_fifo_config_tx_thresh

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_target_fifo_config_acq_thresh

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ovrd_txovrden

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ovrd_sclval

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ovrd_sdaval

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_timing0_thigh

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_timing0_tlow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_timing1_t_r

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.71 100.00 98.85 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_fdata_start
tb.dut.u_reg.u_fdata_stop
tb.dut.u_reg.u_fdata_readb
tb.dut.u_reg.u_fdata_rcont
tb.dut.u_reg.u_fdata_nakok
tb.dut.u_reg.u_fifo_ctrl_rxrst
tb.dut.u_reg.u_fifo_ctrl_fmtrst
tb.dut.u_reg.u_fifo_ctrl_acqrst
tb.dut.u_reg.u_fifo_ctrl_txrst
tb.dut.u_reg.u_host_fifo_config_rx_thresh
tb.dut.u_reg.u_host_fifo_config_fmt_thresh
tb.dut.u_reg.u_target_fifo_config_tx_thresh
tb.dut.u_reg.u_target_fifo_config_acq_thresh
tb.dut.u_reg.u_ovrd_txovrden
tb.dut.u_reg.u_ovrd_sclval
tb.dut.u_reg.u_ovrd_sdaval
tb.dut.u_reg.u_timing0_thigh
tb.dut.u_reg.u_timing0_tlow
tb.dut.u_reg.u_timing1_t_r
Line Coverage for Instance : tb.dut.u_reg.u_fdata_start
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T2 T3 T4  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T2 T3 T4  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fdata_start
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_fdata_start
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fdata_stop
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T2 T3 T4  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T2 T3 T4  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fdata_stop
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_fdata_stop
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fdata_readb
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T2 T3 T4  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T2 T3 T4  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fdata_readb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_fdata_readb
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fdata_rcont
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T2 T3 T4  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T2 T3 T4  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fdata_rcont
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_fdata_rcont
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fdata_nakok
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T2 T3 T4  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T2 T3 T4  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fdata_nakok
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_fdata_nakok
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_fmtrst
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_fmtrst
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_fmtrst
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_acqrst
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_acqrst
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_acqrst
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_rx_thresh
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_rx_thresh
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_rx_thresh
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_fmt_thresh
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_fmt_thresh
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_host_fifo_config_fmt_thresh
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_tx_thresh
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_tx_thresh
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_tx_thresh
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_acq_thresh
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_acq_thresh
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_target_fifo_config_acq_thresh
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ovrd_txovrden
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T75 T101  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T75 T101  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_ovrd_txovrden
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T75,T101

Branch Coverage for Instance : tb.dut.u_reg.u_ovrd_txovrden
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T75,T101
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T75,T101
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ovrd_sclval
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T75 T101  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T75 T101  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_ovrd_sclval
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T75,T101

Branch Coverage for Instance : tb.dut.u_reg.u_ovrd_sclval
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T75,T101
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T75,T101
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ovrd_sdaval
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T75 T101  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T75 T101  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_ovrd_sdaval
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T75,T101

Branch Coverage for Instance : tb.dut.u_reg.u_ovrd_sdaval
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T75,T101
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T75,T101
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timing0_thigh
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_timing0_thigh
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_timing0_thigh
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timing0_tlow
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_timing0_tlow
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_timing0_tlow
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timing1_t_r
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T3 T4 T5  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T3 T4 T5  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_timing1_t_r
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_timing1_t_r
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3