| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.308229045 |
|
|
Sep 04 02:53:26 AM UTC 24 |
Sep 04 02:53:35 AM UTC 24 |
363166680 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.1467209814 |
|
|
Sep 04 02:53:04 AM UTC 24 |
Sep 04 02:53:35 AM UTC 24 |
659139396 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.3677956281 |
|
|
Sep 04 02:52:19 AM UTC 24 |
Sep 04 02:53:36 AM UTC 24 |
12881675730 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.3864119569 |
|
|
Sep 04 02:53:34 AM UTC 24 |
Sep 04 02:53:37 AM UTC 24 |
100246051 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1381961403 |
|
|
Sep 04 02:52:41 AM UTC 24 |
Sep 04 02:53:37 AM UTC 24 |
5367620485 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2093799045 |
|
|
Sep 04 02:53:22 AM UTC 24 |
Sep 04 02:53:38 AM UTC 24 |
2837212516 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2023076006 |
|
|
Sep 04 02:53:36 AM UTC 24 |
Sep 04 02:53:39 AM UTC 24 |
44135795 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.283562786 |
|
|
Sep 04 02:53:37 AM UTC 24 |
Sep 04 02:53:44 AM UTC 24 |
183224456 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.1837800293 |
|
|
Sep 04 02:52:35 AM UTC 24 |
Sep 04 02:53:45 AM UTC 24 |
11458283798 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.627429968 |
|
|
Sep 04 02:51:45 AM UTC 24 |
Sep 04 02:53:45 AM UTC 24 |
22312938049 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2853335645 |
|
|
Sep 04 02:52:55 AM UTC 24 |
Sep 04 02:53:49 AM UTC 24 |
14051619308 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.1347231930 |
|
|
Sep 04 02:53:35 AM UTC 24 |
Sep 04 02:53:49 AM UTC 24 |
182000912 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.1768023677 |
|
|
Sep 04 02:53:34 AM UTC 24 |
Sep 04 02:53:49 AM UTC 24 |
500462422 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.413347785 |
|
|
Sep 04 02:55:16 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
8443100271 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.2616574634 |
|
|
Sep 04 02:51:28 AM UTC 24 |
Sep 04 02:53:53 AM UTC 24 |
14856811347 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.443991307 |
|
|
Sep 04 02:53:53 AM UTC 24 |
Sep 04 02:53:56 AM UTC 24 |
404395580 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.883430005 |
|
|
Sep 04 02:53:46 AM UTC 24 |
Sep 04 02:53:56 AM UTC 24 |
1437340701 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2800718906 |
|
|
Sep 04 02:52:53 AM UTC 24 |
Sep 04 02:53:56 AM UTC 24 |
1980342301 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2455681216 |
|
|
Sep 04 02:53:04 AM UTC 24 |
Sep 04 02:53:57 AM UTC 24 |
1558673218 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3955977101 |
|
|
Sep 04 02:53:54 AM UTC 24 |
Sep 04 02:53:58 AM UTC 24 |
213094457 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2542868689 |
|
|
Sep 04 02:53:40 AM UTC 24 |
Sep 04 02:53:59 AM UTC 24 |
1186879840 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1571898466 |
|
|
Sep 04 02:49:26 AM UTC 24 |
Sep 04 02:53:59 AM UTC 24 |
6338847619 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1244221463 |
|
|
Sep 04 02:53:50 AM UTC 24 |
Sep 04 02:54:01 AM UTC 24 |
9213243479 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2543764768 |
|
|
Sep 04 02:53:58 AM UTC 24 |
Sep 04 02:54:01 AM UTC 24 |
334006955 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1460885829 |
|
|
Sep 04 02:53:54 AM UTC 24 |
Sep 04 02:54:01 AM UTC 24 |
471976887 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.1002801789 |
|
|
Sep 04 02:50:38 AM UTC 24 |
Sep 04 02:54:01 AM UTC 24 |
13961486987 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.3518602278 |
|
|
Sep 04 02:54:00 AM UTC 24 |
Sep 04 02:54:04 AM UTC 24 |
145594162 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3363237697 |
|
|
Sep 04 02:53:58 AM UTC 24 |
Sep 04 02:54:04 AM UTC 24 |
706812980 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.3819228173 |
|
|
Sep 04 02:53:29 AM UTC 24 |
Sep 04 02:54:04 AM UTC 24 |
6601443358 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2242644463 |
|
|
Sep 04 02:53:59 AM UTC 24 |
Sep 04 02:54:05 AM UTC 24 |
376698369 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.789856171 |
|
|
Sep 04 02:54:02 AM UTC 24 |
Sep 04 02:54:06 AM UTC 24 |
501424226 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1349714520 |
|
|
Sep 04 02:54:00 AM UTC 24 |
Sep 04 02:54:06 AM UTC 24 |
2291078806 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.1817302134 |
|
|
Sep 04 02:54:02 AM UTC 24 |
Sep 04 02:54:06 AM UTC 24 |
2589563455 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2494914275 |
|
|
Sep 04 02:54:05 AM UTC 24 |
Sep 04 02:54:06 AM UTC 24 |
37654815 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.271382753 |
|
|
Sep 04 02:54:02 AM UTC 24 |
Sep 04 02:54:07 AM UTC 24 |
405389271 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.2015139834 |
|
|
Sep 04 02:54:02 AM UTC 24 |
Sep 04 02:54:07 AM UTC 24 |
512501378 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_override.3179661435 |
|
|
Sep 04 02:54:06 AM UTC 24 |
Sep 04 02:54:08 AM UTC 24 |
73169899 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.4281296168 |
|
|
Sep 04 02:53:46 AM UTC 24 |
Sep 04 02:54:09 AM UTC 24 |
3530771686 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.623728341 |
|
|
Sep 04 02:54:02 AM UTC 24 |
Sep 04 02:54:09 AM UTC 24 |
291099892 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.2428299428 |
|
|
Sep 04 02:54:07 AM UTC 24 |
Sep 04 02:54:10 AM UTC 24 |
454961665 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.361191192 |
|
|
Sep 04 02:54:08 AM UTC 24 |
Sep 04 02:54:11 AM UTC 24 |
62583224 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.1952863748 |
|
|
Sep 04 02:53:40 AM UTC 24 |
Sep 04 02:54:12 AM UTC 24 |
37952706054 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2261239705 |
|
|
Sep 04 02:54:11 AM UTC 24 |
Sep 04 02:54:14 AM UTC 24 |
117010729 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.157554445 |
|
|
Sep 04 02:53:34 AM UTC 24 |
Sep 04 02:54:16 AM UTC 24 |
1604716793 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.4028705761 |
|
|
Sep 04 02:53:04 AM UTC 24 |
Sep 04 02:54:16 AM UTC 24 |
43059790307 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.331050431 |
|
|
Sep 04 02:54:07 AM UTC 24 |
Sep 04 02:54:16 AM UTC 24 |
2024222367 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2414514079 |
|
|
Sep 04 02:53:37 AM UTC 24 |
Sep 04 02:54:18 AM UTC 24 |
643967295 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.2171727123 |
|
|
Sep 04 02:46:14 AM UTC 24 |
Sep 04 02:54:22 AM UTC 24 |
49536006837 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.3216472154 |
|
|
Sep 04 02:54:12 AM UTC 24 |
Sep 04 02:54:23 AM UTC 24 |
2747981545 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.1735427766 |
|
|
Sep 04 02:54:17 AM UTC 24 |
Sep 04 02:54:26 AM UTC 24 |
4333782430 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.4206950622 |
|
|
Sep 04 02:49:32 AM UTC 24 |
Sep 04 02:54:26 AM UTC 24 |
19936416242 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2058590386 |
|
|
Sep 04 02:54:24 AM UTC 24 |
Sep 04 02:54:27 AM UTC 24 |
484061294 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.911595917 |
|
|
Sep 04 02:54:25 AM UTC 24 |
Sep 04 02:54:29 AM UTC 24 |
184339240 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.3265249046 |
|
|
Sep 04 02:54:18 AM UTC 24 |
Sep 04 02:54:29 AM UTC 24 |
1290183851 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2364502035 |
|
|
Sep 04 02:54:30 AM UTC 24 |
Sep 04 02:54:34 AM UTC 24 |
219521976 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.862478432 |
|
|
Sep 04 02:52:52 AM UTC 24 |
Sep 04 02:54:35 AM UTC 24 |
6269807247 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3082006970 |
|
|
Sep 04 02:53:18 AM UTC 24 |
Sep 04 02:54:35 AM UTC 24 |
24219191967 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3984449292 |
|
|
Sep 04 02:54:07 AM UTC 24 |
Sep 04 02:54:35 AM UTC 24 |
1797014123 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_perf.1620676526 |
|
|
Sep 04 02:54:28 AM UTC 24 |
Sep 04 02:54:36 AM UTC 24 |
8017581842 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2291379949 |
|
|
Sep 04 02:51:47 AM UTC 24 |
Sep 04 02:54:37 AM UTC 24 |
8963546456 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1070837795 |
|
|
Sep 04 02:54:08 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
7302460884 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.45288569 |
|
|
Sep 04 02:54:15 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
1788685288 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.2970464763 |
|
|
Sep 04 02:54:10 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
5251593821 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.1671283786 |
|
|
Sep 04 02:54:36 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
48801776 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_mode_toggle.3476574094 |
|
|
Sep 04 02:54:30 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
209662627 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.4050129365 |
|
|
Sep 04 02:54:36 AM UTC 24 |
Sep 04 02:54:39 AM UTC 24 |
131397731 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1602581050 |
|
|
Sep 04 02:54:29 AM UTC 24 |
Sep 04 02:54:40 AM UTC 24 |
985717167 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.3803291887 |
|
|
Sep 04 02:54:36 AM UTC 24 |
Sep 04 02:54:41 AM UTC 24 |
570607281 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1264773106 |
|
|
Sep 04 02:54:40 AM UTC 24 |
Sep 04 02:54:42 AM UTC 24 |
17902539 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3783455791 |
|
|
Sep 04 02:54:37 AM UTC 24 |
Sep 04 02:54:42 AM UTC 24 |
1699680753 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_override.2725314596 |
|
|
Sep 04 02:54:41 AM UTC 24 |
Sep 04 02:54:43 AM UTC 24 |
41683696 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2696759120 |
|
|
Sep 04 02:54:35 AM UTC 24 |
Sep 04 02:54:43 AM UTC 24 |
851714556 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.2632693435 |
|
|
Sep 04 02:55:37 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
3619808345 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.2814655198 |
|
|
Sep 04 02:54:38 AM UTC 24 |
Sep 04 02:54:43 AM UTC 24 |
1053149394 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.3933154667 |
|
|
Sep 04 02:53:35 AM UTC 24 |
Sep 04 02:54:44 AM UTC 24 |
5673268715 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1855907365 |
|
|
Sep 04 02:54:40 AM UTC 24 |
Sep 04 02:54:44 AM UTC 24 |
2112113830 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.1392224822 |
|
|
Sep 04 02:54:42 AM UTC 24 |
Sep 04 02:54:44 AM UTC 24 |
278605048 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1924420850 |
|
|
Sep 04 02:54:07 AM UTC 24 |
Sep 04 02:54:45 AM UTC 24 |
5781146742 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1281866925 |
|
|
Sep 04 02:53:45 AM UTC 24 |
Sep 04 02:54:46 AM UTC 24 |
1886879197 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1519873006 |
|
|
Sep 04 02:54:46 AM UTC 24 |
Sep 04 02:54:50 AM UTC 24 |
381462142 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2581740639 |
|
|
Sep 04 02:54:42 AM UTC 24 |
Sep 04 02:54:50 AM UTC 24 |
1348872690 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1994547643 |
|
|
Sep 04 02:54:05 AM UTC 24 |
Sep 04 02:54:51 AM UTC 24 |
1913553635 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.1167729004 |
|
|
Sep 04 02:54:44 AM UTC 24 |
Sep 04 02:54:51 AM UTC 24 |
334673424 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.243292087 |
|
|
Sep 04 02:54:43 AM UTC 24 |
Sep 04 02:54:57 AM UTC 24 |
208957138 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.4080298180 |
|
|
Sep 04 02:54:51 AM UTC 24 |
Sep 04 02:55:01 AM UTC 24 |
1871260486 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.2849645623 |
|
|
Sep 04 02:54:50 AM UTC 24 |
Sep 04 02:55:02 AM UTC 24 |
4008753681 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1957884054 |
|
|
Sep 04 02:54:52 AM UTC 24 |
Sep 04 02:55:02 AM UTC 24 |
2052897039 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.70069777 |
|
|
Sep 04 02:55:00 AM UTC 24 |
Sep 04 02:55:04 AM UTC 24 |
442478943 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3036407167 |
|
|
Sep 04 02:55:02 AM UTC 24 |
Sep 04 02:55:04 AM UTC 24 |
134265595 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2951825670 |
|
|
Sep 04 02:53:50 AM UTC 24 |
Sep 04 02:55:05 AM UTC 24 |
21923452054 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.431051616 |
|
|
Sep 04 02:52:54 AM UTC 24 |
Sep 04 02:55:06 AM UTC 24 |
8172932180 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.1882173233 |
|
|
Sep 04 02:53:58 AM UTC 24 |
Sep 04 02:55:07 AM UTC 24 |
109674403509 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2347442058 |
|
|
Sep 04 02:54:40 AM UTC 24 |
Sep 04 02:55:08 AM UTC 24 |
3752290779 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.519638865 |
|
|
Sep 04 02:55:05 AM UTC 24 |
Sep 04 02:55:08 AM UTC 24 |
275690672 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3996903392 |
|
|
Sep 04 02:54:46 AM UTC 24 |
Sep 04 02:55:09 AM UTC 24 |
744019153 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.2387552075 |
|
|
Sep 04 02:54:46 AM UTC 24 |
Sep 04 02:56:20 AM UTC 24 |
44013956581 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3332000726 |
|
|
Sep 04 02:54:47 AM UTC 24 |
Sep 04 02:55:10 AM UTC 24 |
978122357 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3421980621 |
|
|
Sep 04 02:55:08 AM UTC 24 |
Sep 04 02:55:11 AM UTC 24 |
638888183 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3501163525 |
|
|
Sep 04 02:55:05 AM UTC 24 |
Sep 04 02:55:14 AM UTC 24 |
2183315783 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3081028719 |
|
|
Sep 04 02:55:03 AM UTC 24 |
Sep 04 02:55:14 AM UTC 24 |
2031172127 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1480230914 |
|
|
Sep 04 02:55:07 AM UTC 24 |
Sep 04 02:55:14 AM UTC 24 |
467553987 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.1202847843 |
|
|
Sep 04 02:55:12 AM UTC 24 |
Sep 04 02:55:15 AM UTC 24 |
133153517 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.922276963 |
|
|
Sep 04 02:55:09 AM UTC 24 |
Sep 04 02:55:15 AM UTC 24 |
160095441 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.2893816496 |
|
|
Sep 04 02:55:10 AM UTC 24 |
Sep 04 02:55:15 AM UTC 24 |
762025673 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1000126016 |
|
|
Sep 04 02:55:14 AM UTC 24 |
Sep 04 02:55:16 AM UTC 24 |
17933069 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2266923123 |
|
|
Sep 04 02:55:12 AM UTC 24 |
Sep 04 02:55:16 AM UTC 24 |
4015850751 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.2174977121 |
|
|
Sep 04 02:55:11 AM UTC 24 |
Sep 04 02:55:17 AM UTC 24 |
550978225 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_override.349753556 |
|
|
Sep 04 02:55:15 AM UTC 24 |
Sep 04 02:55:17 AM UTC 24 |
45969489 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.3586184381 |
|
|
Sep 04 02:55:16 AM UTC 24 |
Sep 04 02:55:19 AM UTC 24 |
343881178 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.2900581697 |
|
|
Sep 04 02:54:17 AM UTC 24 |
Sep 04 02:55:21 AM UTC 24 |
1485607121 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1320609817 |
|
|
Sep 04 02:54:44 AM UTC 24 |
Sep 04 02:55:23 AM UTC 24 |
4166016417 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.671641226 |
|
|
Sep 04 02:55:17 AM UTC 24 |
Sep 04 02:55:28 AM UTC 24 |
137849666 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.475513273 |
|
|
Sep 04 02:54:07 AM UTC 24 |
Sep 04 02:55:30 AM UTC 24 |
3355899975 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.4206556104 |
|
|
Sep 04 02:55:15 AM UTC 24 |
Sep 04 02:55:33 AM UTC 24 |
2123345746 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.4053706870 |
|
|
Sep 04 02:38:45 AM UTC 24 |
Sep 04 02:55:33 AM UTC 24 |
60312693804 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2705224786 |
|
|
Sep 04 02:54:52 AM UTC 24 |
Sep 04 02:55:36 AM UTC 24 |
9865531419 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/43.i2c_host_stress_all.3129049771 |
|
|
Sep 04 02:51:51 AM UTC 24 |
Sep 04 02:55:36 AM UTC 24 |
34963849330 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.2449567277 |
|
|
Sep 04 02:55:18 AM UTC 24 |
Sep 04 02:55:38 AM UTC 24 |
3634831745 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.2601572099 |
|
|
Sep 04 02:55:16 AM UTC 24 |
Sep 04 02:55:38 AM UTC 24 |
3720618048 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.3075163744 |
|
|
Sep 04 02:55:22 AM UTC 24 |
Sep 04 02:55:39 AM UTC 24 |
424459552 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1127476443 |
|
|
Sep 04 02:55:39 AM UTC 24 |
Sep 04 02:55:43 AM UTC 24 |
704390414 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.28943976 |
|
|
Sep 04 02:53:09 AM UTC 24 |
Sep 04 02:55:45 AM UTC 24 |
12767092249 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2213881912 |
|
|
Sep 04 02:55:29 AM UTC 24 |
Sep 04 02:55:45 AM UTC 24 |
3687142531 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1882255485 |
|
|
Sep 04 02:54:17 AM UTC 24 |
Sep 04 02:55:46 AM UTC 24 |
8807080968 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.2996286476 |
|
|
Sep 04 02:55:44 AM UTC 24 |
Sep 04 02:55:46 AM UTC 24 |
241934911 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1430121845 |
|
|
Sep 04 02:55:37 AM UTC 24 |
Sep 04 02:55:48 AM UTC 24 |
854933145 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1141295683 |
|
|
Sep 04 02:55:19 AM UTC 24 |
Sep 04 02:55:49 AM UTC 24 |
2179151337 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.4237505795 |
|
|
Sep 04 02:55:47 AM UTC 24 |
Sep 04 02:55:51 AM UTC 24 |
149760731 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.1647653159 |
|
|
Sep 04 02:55:47 AM UTC 24 |
Sep 04 02:55:52 AM UTC 24 |
351700732 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.1770388829 |
|
|
Sep 04 02:55:38 AM UTC 24 |
Sep 04 02:55:52 AM UTC 24 |
6057251569 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_perf.847193588 |
|
|
Sep 04 02:55:45 AM UTC 24 |
Sep 04 02:55:52 AM UTC 24 |
473747754 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2469768721 |
|
|
Sep 04 02:55:50 AM UTC 24 |
Sep 04 02:55:53 AM UTC 24 |
839119509 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1569836391 |
|
|
Sep 04 02:55:51 AM UTC 24 |
Sep 04 02:55:55 AM UTC 24 |
641621470 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.3915419565 |
|
|
Sep 04 02:55:46 AM UTC 24 |
Sep 04 02:55:57 AM UTC 24 |
5630524670 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1101326364 |
|
|
Sep 04 02:46:50 AM UTC 24 |
Sep 04 02:55:57 AM UTC 24 |
45078455733 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.3018246626 |
|
|
Sep 04 02:55:52 AM UTC 24 |
Sep 04 02:55:58 AM UTC 24 |
213122143 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.3758210131 |
|
|
Sep 04 02:55:53 AM UTC 24 |
Sep 04 02:55:59 AM UTC 24 |
2041764538 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.68212968 |
|
|
Sep 04 02:55:56 AM UTC 24 |
Sep 04 02:55:59 AM UTC 24 |
681608559 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.2519574688 |
|
|
Sep 04 02:55:53 AM UTC 24 |
Sep 04 02:55:59 AM UTC 24 |
2233128448 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.791300943 |
|
|
Sep 04 02:55:55 AM UTC 24 |
Sep 04 02:56:00 AM UTC 24 |
1515579978 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3436885532 |
|
|
Sep 04 02:55:58 AM UTC 24 |
Sep 04 02:56:00 AM UTC 24 |
19096901 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1612470755 |
|
|
Sep 04 02:55:33 AM UTC 24 |
Sep 04 02:56:05 AM UTC 24 |
5501002587 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.2861991269 |
|
|
Sep 04 02:49:30 AM UTC 24 |
Sep 04 02:56:06 AM UTC 24 |
40984512743 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_perf.3957380293 |
|
|
Sep 04 02:53:36 AM UTC 24 |
Sep 04 02:56:08 AM UTC 24 |
12615845694 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.4073937741 |
|
|
Sep 04 02:55:34 AM UTC 24 |
Sep 04 02:56:12 AM UTC 24 |
3297951153 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.363588251 |
|
|
Sep 04 02:55:32 AM UTC 24 |
Sep 04 02:56:18 AM UTC 24 |
30964795222 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2750538641 |
|
|
Sep 04 02:55:48 AM UTC 24 |
Sep 04 02:56:24 AM UTC 24 |
5843850547 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.847498627 |
|
|
Sep 04 02:51:57 AM UTC 24 |
Sep 04 02:56:26 AM UTC 24 |
21012487990 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.973874758 |
|
|
Sep 04 02:54:08 AM UTC 24 |
Sep 04 02:56:38 AM UTC 24 |
2935632020 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1566880364 |
|
|
Sep 04 02:54:13 AM UTC 24 |
Sep 04 02:56:51 AM UTC 24 |
55826944248 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2989615995 |
|
|
Sep 04 02:54:44 AM UTC 24 |
Sep 04 02:56:52 AM UTC 24 |
26092327988 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_perf.1798009167 |
|
|
Sep 04 02:55:18 AM UTC 24 |
Sep 04 02:57:12 AM UTC 24 |
5308880014 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.3679981050 |
|
|
Sep 04 02:36:57 AM UTC 24 |
Sep 04 02:57:41 AM UTC 24 |
35679686351 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.47065482 |
|
|
Sep 04 02:53:32 AM UTC 24 |
Sep 04 02:57:51 AM UTC 24 |
9946366377 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3246837421 |
|
|
Sep 04 02:54:41 AM UTC 24 |
Sep 04 02:57:53 AM UTC 24 |
2753764790 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.2766694650 |
|
|
Sep 04 02:53:03 AM UTC 24 |
Sep 04 02:58:40 AM UTC 24 |
11175099729 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.789493294 |
|
|
Sep 04 02:55:17 AM UTC 24 |
Sep 04 02:58:54 AM UTC 24 |
3474897521 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/43.i2c_host_perf.875623510 |
|
|
Sep 04 02:51:47 AM UTC 24 |
Sep 04 02:58:56 AM UTC 24 |
25367511588 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2739749392 |
|
|
Sep 04 02:55:16 AM UTC 24 |
Sep 04 02:59:02 AM UTC 24 |
12448747405 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.2985608091 |
|
|
Sep 04 02:44:25 AM UTC 24 |
Sep 04 02:59:04 AM UTC 24 |
23164110381 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.2555526472 |
|
|
Sep 04 02:55:46 AM UTC 24 |
Sep 04 02:59:21 AM UTC 24 |
26271753542 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3308822332 |
|
|
Sep 04 02:54:41 AM UTC 24 |
Sep 04 02:59:47 AM UTC 24 |
21399005685 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.219606827 |
|
|
Sep 04 02:50:23 AM UTC 24 |
Sep 04 02:59:58 AM UTC 24 |
39494661470 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.2972979269 |
|
|
Sep 04 02:51:23 AM UTC 24 |
Sep 04 03:00:24 AM UTC 24 |
44740278578 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1587571734 |
|
|
Sep 04 02:55:03 AM UTC 24 |
Sep 04 03:02:23 AM UTC 24 |
29993267123 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/14.i2c_host_stress_all.1399881699 |
|
|
Sep 04 02:36:08 AM UTC 24 |
Sep 04 03:02:41 AM UTC 24 |
90926968448 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.1358757492 |
|
|
Sep 04 02:52:28 AM UTC 24 |
Sep 04 03:03:58 AM UTC 24 |
45939266933 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/42.i2c_host_stress_all.393657254 |
|
|
Sep 04 02:51:20 AM UTC 24 |
Sep 04 03:06:27 AM UTC 24 |
25739956692 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2906711120 |
|
|
Sep 04 02:48:55 AM UTC 24 |
Sep 04 03:07:18 AM UTC 24 |
61408624222 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.3148931464 |
|
|
Sep 04 02:54:28 AM UTC 24 |
Sep 04 03:07:49 AM UTC 24 |
46462625344 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.3887407183 |
|
|
Sep 04 02:42:52 AM UTC 24 |
Sep 04 03:08:00 AM UTC 24 |
67844590919 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.859088363 |
|
|
Sep 04 02:52:24 AM UTC 24 |
Sep 04 03:08:15 AM UTC 24 |
133379410491 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.1087984686 |
|
|
Sep 04 02:43:24 AM UTC 24 |
Sep 04 03:08:26 AM UTC 24 |
38462700430 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2886228078 |
|
|
Sep 04 02:41:41 AM UTC 24 |
Sep 04 03:08:39 AM UTC 24 |
70456187824 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.1697569749 |
|
|
Sep 04 02:47:03 AM UTC 24 |
Sep 04 03:10:18 AM UTC 24 |
62360372931 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/31.i2c_host_perf.2672764811 |
|
|
Sep 04 02:44:25 AM UTC 24 |
Sep 04 03:10:47 AM UTC 24 |
73374921739 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1357887518 |
|
|
Sep 04 02:54:44 AM UTC 24 |
Sep 04 03:14:01 AM UTC 24 |
26024688882 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.4037396326 |
|
|
Sep 04 02:54:11 AM UTC 24 |
Sep 04 03:16:10 AM UTC 24 |
65590163052 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/default/36.i2c_host_perf.2112884157 |
|
|
Sep 04 02:47:16 AM UTC 24 |
Sep 04 03:21:08 AM UTC 24 |
49687278899 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1310535737 |
|
|
Sep 04 02:56:26 AM UTC 24 |
Sep 04 02:56:28 AM UTC 24 |
16960725 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3818256958 |
|
|
Sep 04 02:55:59 AM UTC 24 |
Sep 04 02:56:02 AM UTC 24 |
60721421 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.762849726 |
|
|
Sep 04 02:56:00 AM UTC 24 |
Sep 04 02:56:02 AM UTC 24 |
41598247 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.3238842861 |
|
|
Sep 04 02:55:59 AM UTC 24 |
Sep 04 02:56:02 AM UTC 24 |
69855549 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.17172650 |
|
|
Sep 04 02:56:00 AM UTC 24 |
Sep 04 02:56:02 AM UTC 24 |
17628741 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1255542899 |
|
|
Sep 04 02:56:00 AM UTC 24 |
Sep 04 02:56:02 AM UTC 24 |
71227262 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1880824052 |
|
|
Sep 04 02:56:00 AM UTC 24 |
Sep 04 02:56:03 AM UTC 24 |
94198660 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1861823103 |
|
|
Sep 04 02:56:02 AM UTC 24 |
Sep 04 02:56:05 AM UTC 24 |
120507033 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2071603569 |
|
|
Sep 04 02:56:02 AM UTC 24 |
Sep 04 02:56:05 AM UTC 24 |
180337125 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2706187466 |
|
|
Sep 04 02:56:00 AM UTC 24 |
Sep 04 02:56:05 AM UTC 24 |
143088497 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.371282344 |
|
|
Sep 04 02:56:04 AM UTC 24 |
Sep 04 02:56:06 AM UTC 24 |
16818343 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3935838129 |
|
|
Sep 04 02:56:04 AM UTC 24 |
Sep 04 02:56:06 AM UTC 24 |
52462164 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.3036269079 |
|
|
Sep 04 02:56:04 AM UTC 24 |
Sep 04 02:56:07 AM UTC 24 |
48652574 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1553970128 |
|
|
Sep 04 02:56:04 AM UTC 24 |
Sep 04 02:56:07 AM UTC 24 |
127227908 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.1765146901 |
|
|
Sep 04 02:56:06 AM UTC 24 |
Sep 04 02:56:08 AM UTC 24 |
39099177 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1942863478 |
|
|
Sep 04 02:56:06 AM UTC 24 |
Sep 04 02:56:08 AM UTC 24 |
133636812 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.2609698866 |
|
|
Sep 04 02:56:07 AM UTC 24 |
Sep 04 02:56:09 AM UTC 24 |
29465849 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.910290242 |
|
|
Sep 04 02:56:07 AM UTC 24 |
Sep 04 02:56:10 AM UTC 24 |
59377958 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3978400602 |
|
|
Sep 04 02:56:06 AM UTC 24 |
Sep 04 02:56:10 AM UTC 24 |
220313121 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1909248873 |
|
|
Sep 04 02:56:09 AM UTC 24 |
Sep 04 02:56:11 AM UTC 24 |
33405014 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.771046873 |
|
|
Sep 04 02:56:09 AM UTC 24 |
Sep 04 02:56:11 AM UTC 24 |
26928443 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3597531525 |
|
|
Sep 04 02:56:07 AM UTC 24 |
Sep 04 02:56:11 AM UTC 24 |
81943996 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.4136121821 |
|
|
Sep 04 02:56:07 AM UTC 24 |
Sep 04 02:56:11 AM UTC 24 |
124435711 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1604260278 |
|
|
Sep 04 02:56:10 AM UTC 24 |
Sep 04 02:56:12 AM UTC 24 |
33945349 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.942116197 |
|
|
Sep 04 02:56:06 AM UTC 24 |
Sep 04 02:56:12 AM UTC 24 |
390812090 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.1621181656 |
|
|
Sep 04 02:56:11 AM UTC 24 |
Sep 04 02:56:13 AM UTC 24 |
48862022 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2865255286 |
|
|
Sep 04 02:56:09 AM UTC 24 |
Sep 04 02:56:13 AM UTC 24 |
63681361 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3076569138 |
|
|
Sep 04 02:56:10 AM UTC 24 |
Sep 04 02:56:13 AM UTC 24 |
98430982 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4092408771 |
|
|
Sep 04 02:56:11 AM UTC 24 |
Sep 04 02:56:14 AM UTC 24 |
41590843 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.4293901425 |
|
|
Sep 04 02:56:11 AM UTC 24 |
Sep 04 02:56:14 AM UTC 24 |
125735259 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.4176969981 |
|
|
Sep 04 02:56:12 AM UTC 24 |
Sep 04 02:56:14 AM UTC 24 |
92146206 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1339552007 |
|
|
Sep 04 02:56:12 AM UTC 24 |
Sep 04 02:56:14 AM UTC 24 |
19974259 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2674108782 |
|
|
Sep 04 02:56:11 AM UTC 24 |
Sep 04 02:56:15 AM UTC 24 |
284207313 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1254256167 |
|
|
Sep 04 02:56:14 AM UTC 24 |
Sep 04 02:56:16 AM UTC 24 |
106245682 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1360781633 |
|
|
Sep 04 02:56:14 AM UTC 24 |
Sep 04 02:56:16 AM UTC 24 |
141104050 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3694594508 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:17 AM UTC 24 |
46854996 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.2561227881 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:17 AM UTC 24 |
56951342 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.3172581710 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:17 AM UTC 24 |
27876040 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.1949207411 |
|
|
Sep 04 02:56:14 AM UTC 24 |
Sep 04 02:56:17 AM UTC 24 |
96576042 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1092443956 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:18 AM UTC 24 |
293599442 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.291934520 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:18 AM UTC 24 |
350369632 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3657682383 |
|
|
Sep 04 02:56:17 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
93910382 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.128804332 |
|
|
Sep 04 02:56:17 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
44322888 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3165908494 |
|
|
Sep 04 02:56:16 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
102046023 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.3662895958 |
|
|
Sep 04 02:56:12 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
218721148 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1124962222 |
|
|
Sep 04 02:56:15 AM UTC 24 |
Sep 04 02:56:19 AM UTC 24 |
1144807597 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2251534263 |
|
|
Sep 04 02:56:18 AM UTC 24 |
Sep 04 02:56:20 AM UTC 24 |
20266897 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.2176991200 |
|
|
Sep 04 02:56:18 AM UTC 24 |
Sep 04 02:56:20 AM UTC 24 |
24720672 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2074812045 |
|
|
Sep 04 02:56:18 AM UTC 24 |
Sep 04 02:56:21 AM UTC 24 |
296330042 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.200823888 |
|
|
Sep 04 02:56:19 AM UTC 24 |
Sep 04 02:56:21 AM UTC 24 |
32881443 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3671565876 |
|
|
Sep 04 02:56:19 AM UTC 24 |
Sep 04 02:56:22 AM UTC 24 |
43858785 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.504103730 |
|
|
Sep 04 02:56:20 AM UTC 24 |
Sep 04 02:56:22 AM UTC 24 |
31003624 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3381834776 |
|
|
Sep 04 02:56:20 AM UTC 24 |
Sep 04 02:56:22 AM UTC 24 |
28207635 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2185843435 |
|
|
Sep 04 02:56:20 AM UTC 24 |
Sep 04 02:56:22 AM UTC 24 |
63195036 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2341873513 |
|
|
Sep 04 02:56:18 AM UTC 24 |
Sep 04 02:56:22 AM UTC 24 |
168628833 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1972053823 |
|
|
Sep 04 02:56:19 AM UTC 24 |
Sep 04 02:56:23 AM UTC 24 |
1077391634 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.2618093932 |
|
|
Sep 04 02:56:20 AM UTC 24 |
Sep 04 02:56:23 AM UTC 24 |
149629664 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2901999656 |
|
|
Sep 04 02:56:21 AM UTC 24 |
Sep 04 02:56:23 AM UTC 24 |
67032977 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.2022378691 |
|
|
Sep 04 02:56:21 AM UTC 24 |
Sep 04 02:56:23 AM UTC 24 |
107795085 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3759912992 |
|
|
Sep 04 02:56:21 AM UTC 24 |
Sep 04 02:56:23 AM UTC 24 |
40746692 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.4182342487 |
|
|
Sep 04 02:56:21 AM UTC 24 |
Sep 04 02:56:24 AM UTC 24 |
249615496 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.785870495 |
|
|
Sep 04 02:56:24 AM UTC 24 |
Sep 04 02:56:28 AM UTC 24 |
44103075 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.2491592033 |
|
|
Sep 04 02:56:21 AM UTC 24 |
Sep 04 02:56:24 AM UTC 24 |
142133696 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4062127338 |
|
|
Sep 04 02:56:22 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
19844602 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.1507285907 |
|
|
Sep 04 02:56:23 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
26396204 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1809631760 |
|
|
Sep 04 02:56:23 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
29086846 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2694709870 |
|
|
Sep 04 02:56:23 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
58957346 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.333158912 |
|
|
Sep 04 02:56:23 AM UTC 24 |
Sep 04 02:56:25 AM UTC 24 |
55416633 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2493164642 |
|
|
Sep 04 02:56:24 AM UTC 24 |
Sep 04 02:56:26 AM UTC 24 |
23679194 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3609434342 |
|
|
Sep 04 02:56:24 AM UTC 24 |
Sep 04 02:56:26 AM UTC 24 |
36193281 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.1126160860 |
|
|
Sep 04 02:56:24 AM UTC 24 |
Sep 04 02:56:26 AM UTC 24 |
22871749 ps |