Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.48	100.00	100.00	93.91			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.29	97.15	89.39	97.22	71.43	94.11	98.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	87.44	96.10	83.68		71.43	91.30	94.69
i2c_csr_assert	93.75						93.75
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	98.65	98.59	97.07	100.00		97.58	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00

68                      
69         1/1            assign alert_test = {
           Tests:       T1 T2 T3 
70                          reg2hw.alert_test.q &
71                          reg2hw.alert_test.qe
72                        };
73                      
74                        for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
75                          prim_alert_sender #(
76                            .AsyncOn(AlertAsyncOn[i]),
77                            .IsFatal(1'b1)
78                          ) u_prim_alert_sender (
79                            .clk_i,
80                            .rst_ni,
81                            .alert_test_i  ( alert_test[i] ),
82                            .alert_req_i   ( alerts[0]     ),
83                            .alert_ack_o   (               ),
84                            .alert_state_o (               ),
85                            .alert_rx_i    ( alert_rx_i[i] ),
86                            .alert_tx_o    ( alert_tx_o[i] )
87                          );
88                        end
89                      
90                        logic scl_int;
91                        logic sda_int;
92                      
93                        i2c_core #(
94                          .InputDelayCycles(InputDelayCycles)
95                        ) i2c_core (
96                          .clk_i,
97                          .rst_ni,
98                          .ram_cfg_i,
99                      
100                         .reg2hw,
101                         .hw2reg,
102                     
103                         .scl_i(cio_scl_i),
104                         .scl_o(scl_int),
105                         .sda_i(cio_sda_i),
106                         .sda_o(sda_int),
107                     
108                         .intr_fmt_threshold_o,
109                         .intr_rx_threshold_o,
110                         .intr_acq_threshold_o,
111                         .intr_rx_overflow_o,
112                         .intr_controller_halt_o,
113                         .intr_scl_interference_o,
114                         .intr_sda_interference_o,
115                         .intr_stretch_timeout_o,
116                         .intr_sda_unstable_o,
117                         .intr_cmd_complete_o,
118                         .intr_tx_stretch_o,
119                         .intr_tx_threshold_o,
120                         .intr_acq_stretch_o,
121                         .intr_unexp_stop_o,
122                         .intr_host_timeout_o
123                       );
124                     
125                       // For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
126                       // Asserting scl or sda high should be equivalent to a tri-state output.
127                       // The output, when enabled, should only assert low.
128                     
129                       assign cio_scl_o = 1'b0;
130                       assign cio_sda_o = 1'b0;
131                     
132        1/1            assign cio_scl_en_o = ~scl_int;
           Tests:       T1 T2 T3 
133        1/1            assign cio_sda_en_o = ~sda_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T100,T101,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T100,T101,T102

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	51	45	88.24
Total Bits	394	370	93.91
Total Bits 0->1	197	185	93.91
Total Bits 1->0	197	185	93.91

Ports	51	45	88.24
Port Bits	394	370	93.91
Port Bits 0->1	197	185	93.91
Port Bits 1->0	197	185	93.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T170,T171	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T195,T196,T197	Yes	T195,T196,T197	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T100,T170,T101	Yes	T100,T170,T101	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T100,T170,T101	Yes	T100,T170,T101	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T1,T8,T11	Yes	T1,T2,T3	OUTPUT
intr_rx_threshold_o	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
intr_acq_threshold_o	Yes	Yes	T49,T50,T172	Yes	T49,T50,T172	OUTPUT
intr_rx_overflow_o	Yes	Yes	T83,T36,T104	Yes	T83,T36,T104	OUTPUT
intr_controller_halt_o	Yes	Yes	T1,T12,T13	Yes	T1,T12,T13	OUTPUT
intr_scl_interference_o	Yes	Yes	T1,T19,T20	Yes	T1,T19,T20	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T19,T20	Yes	T1,T19,T20	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	OUTPUT
intr_sda_unstable_o	Yes	Yes	T19,T20,T22	Yes	T19,T20,T22	OUTPUT
intr_cmd_complete_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
intr_tx_stretch_o	Yes	Yes	T3,T7,T9	Yes	T3,T7,T9	OUTPUT
intr_tx_threshold_o	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	OUTPUT
intr_acq_stretch_o	Yes	Yes	T7,T9,T45	Yes	T7,T9,T45	OUTPUT
intr_unexp_stop_o	Yes	Yes	T49,T50,T123	Yes	T49,T50,T123	OUTPUT
intr_host_timeout_o	Yes	Yes	T45,T77,T78	Yes	T45,T77,T78	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	403567476	403397161	0	0
CioSclEnKnownO_A	403567476	403397161	0	0
CioSclKnownO_A	403567476	403397161	0	0
CioSdaEnKnownO_A	403567476	403397161	0	0
CioSdaKnownO_A	403567476	403397161	0	0
FpvSecCmRegWeOnehotCheck_A	403567476	70	0	0
IntrAcqStretchKnownO_A	403567476	403397161	0	0
IntrAcqWtmkKnownO_A	403567476	403397161	0	0
IntrCommandCompleteKnownO_A	403567476	403397161	0	0
IntrControllerHaltKnownO_A	403567476	403397161	0	0
IntrFmtWtmkKnownO_A	403567476	403397161	0	0
IntrHostTimeoutKnownO_A	403567476	403397161	0	0
IntrRxOflwKnownO_A	403567476	403397161	0	0
IntrRxWtmkKnownO_A	403567476	403397161	0	0
IntrSclInterfKnownO_A	403567476	403397161	0	0
IntrSdaInterfKnownO_A	403567476	403397161	0	0
IntrSdaUnstableKnownO_A	403567476	403397161	0	0
IntrStretchTimeoutKnownO_A	403567476	403397161	0	0
IntrTxStretchKnownO_A	403567476	403397161	0	0
IntrTxWtmkKnownO_A	403567476	403397161	0	0
IntrUnexpStopKnownO_A	403567476	403397161	0	0
TlAReadyKnownO_A	403567476	403397161	0	0
TlDValidKnownO_A	403567476	403397161	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	70	0	0
T12	38422	0	0	0
T21	92323	0	0	0
T37	15443	0	0	0
T43	8574	0	0	0
T75	21574	0	0	0
T76	7023	0	0	0
T156	0	20	0	0
T170	3564	10	0	0
T171	0	10	0	0
T172	28099	0	0	0
T198	0	10	0	0
T199	0	20	0	0
T200	179080	0	0	0
T201	40846	0	0	0

IntrAcqStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrAcqWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrControllerHaltKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrTxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403567476	403397161	0	0
T1	6301	5876	0	0
T2	84174	84094	0	0
T3	17324	17245	0	0
T4	1584	1500	0	0
T5	270398	270348	0	0
T6	15707	15621	0	0
T7	15170	15119	0	0
T8	22887	22798	0	0
T9	115622	115532	0	0
T10	83333	83253	0	0