Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	404309641	0	0	0
ctrl_rd_A	404309641	2926	0	0
host_fifo_config_rd_A	404309641	5449	0	0
host_nack_handler_timeout_rd_A	404309641	1730	0	0
host_timeout_ctrl_rd_A	404309641	1316	0	0
intr_enable_rd_A	404309641	5732	0	0
ovrd_rd_A	404309641	2512	0	0
target_fifo_config_rd_A	404309641	1635	0	0
target_id_rd_A	404309641	2288	0	0
target_timeout_ctrl_rd_A	404309641	1724	0	0
timeout_ctrl_rd_A	404309641	1823	0	0
timing0_rd_A	404309641	1651	0	0
timing1_rd_A	404309641	1607	0	0
timing2_rd_A	404309641	1615	0	0
timing3_rd_A	404309641	1578	0	0
timing4_rd_A	404309641	1520	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	2926	0	0
T107	3291	45	0	0
T108	13154	95	0	0
T109	24046	111	0	0
T110	1727	10	0	0
T111	7657	151	0	0
T112	9489	20	0	0
T113	27126	228	0	0
T114	16026	18	0	0
T115	2718	12	0	0
T116	2505	43	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	5449	0	0
T32	15850	0	0	0
T41	244116	0	0	0
T57	764637	0	0	0
T84	416493	154	0	0
T117	0	224	0	0
T118	0	182	0	0
T119	0	197	0	0
T120	0	214	0	0
T121	0	239	0	0
T122	0	93	0	0
T123	0	227	0	0
T124	0	60	0	0
T125	0	203	0	0
T126	178681	0	0	0
T127	18314	0	0	0
T128	19676	0	0	0
T129	67444	0	0	0
T130	12321	0	0	0
T131	19065	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1730	0	0
T107	3291	43	0	0
T108	13154	44	0	0
T109	24046	163	0	0
T110	1727	6	0	0
T111	7657	32	0	0
T112	9489	41	0	0
T113	27126	229	0	0
T114	16026	40	0	0
T115	2718	6	0	0
T116	2505	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1316	0	0
T107	3291	7	0	0
T108	13154	31	0	0
T109	24046	150	0	0
T110	1727	6	0	0
T111	7657	43	0	0
T112	9489	4	0	0
T113	27126	215	0	0
T114	16026	47	0	0
T115	2718	10	0	0
T116	2505	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	5732	0	0
T40	0	24	0	0
T107	0	13	0	0
T108	0	489	0	0
T109	0	160	0	0
T110	0	3	0	0
T111	0	296	0	0
T123	155885	18	0	0
T132	0	16	0	0
T133	0	29	0	0
T134	0	10	0	0
T135	25236	0	0	0
T136	55208	0	0	0
T137	599169	0	0	0
T138	15997	0	0	0
T139	3543	0	0	0
T140	13404	0	0	0
T141	120652	0	0	0
T142	21720	0	0	0
T143	74794	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	2512	0	0
T69	45692	0	0	0
T83	177325	0	0	0
T102	1070	0	0	0
T144	1895	55	0	0
T145	0	25	0	0
T146	0	32	0	0
T147	0	53	0	0
T148	0	59	0	0
T149	0	51	0	0
T150	0	52	0	0
T151	0	77	0	0
T152	0	81	0	0
T153	0	12	0	0
T154	39588	0	0	0
T155	116355	0	0	0
T156	6760	0	0	0
T157	31264	0	0	0
T158	15307	0	0	0
T159	16177	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1635	0	0
T108	13154	52	0	0
T109	24046	112	0	0
T110	1727	9	0	0
T111	7657	37	0	0
T112	9489	28	0	0
T113	27126	269	0	0
T114	16026	55	0	0
T115	2718	11	0	0
T116	2505	10	0	0
T160	5745	60	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	2288	0	0
T107	3291	15	0	0
T108	13154	106	0	0
T109	24046	174	0	0
T110	1727	7	0	0
T111	7657	100	0	0
T112	9489	36	0	0
T113	27126	213	0	0
T114	16026	18	0	0
T115	2718	8	0	0
T116	2505	32	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1724	0	0
T107	3291	42	0	0
T108	13154	30	0	0
T109	24046	163	0	0
T110	1727	9	0	0
T111	7657	57	0	0
T112	9489	37	0	0
T113	27126	244	0	0
T114	16026	37	0	0
T115	2718	14	0	0
T116	2505	20	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1823	0	0
T107	3291	11	0	0
T108	13154	70	0	0
T109	24046	118	0	0
T111	7657	59	0	0
T112	9489	7	0	0
T113	27126	244	0	0
T114	16026	33	0	0
T115	2718	8	0	0
T116	2505	3	0	0
T160	5745	25	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1651	0	0
T108	13154	69	0	0
T109	24046	125	0	0
T110	1727	6	0	0
T111	7657	51	0	0
T112	9489	40	0	0
T113	27126	253	0	0
T114	16026	29	0	0
T115	2718	3	0	0
T116	2505	14	0	0
T160	5745	79	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1607	0	0
T107	3291	12	0	0
T108	13154	56	0	0
T109	24046	182	0	0
T110	1727	2	0	0
T111	7657	55	0	0
T112	9489	21	0	0
T113	27126	216	0	0
T114	16026	40	0	0
T115	2718	9	0	0
T116	2505	21	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1615	0	0
T107	3291	7	0	0
T108	13154	48	0	0
T109	24046	129	0	0
T110	1727	8	0	0
T111	7657	54	0	0
T112	9489	25	0	0
T113	27126	247	0	0
T114	16026	55	0	0
T115	2718	6	0	0
T116	2505	17	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1578	0	0
T107	3291	15	0	0
T108	13154	84	0	0
T109	24046	114	0	0
T110	1727	3	0	0
T111	7657	58	0	0
T112	9489	13	0	0
T113	27126	212	0	0
T114	16026	28	0	0
T115	2718	14	0	0
T116	2505	13	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404309641	1520	0	0
T107	3291	16	0	0
T108	13154	61	0	0
T109	24046	111	0	0
T110	1727	2	0	0
T111	7657	48	0	0
T112	9489	14	0	0
T113	27126	229	0	0
T114	16026	29	0	0
T115	2718	7	0	0
T116	2505	18	0	0