Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	842829	1			T1	1		T2	2		T3	3
all_values[1]	842829	1			T1	1		T2	2		T3	3
all_values[2]	842829	1			T1	1		T2	2		T3	3
all_values[3]	842829	1			T1	1		T2	2		T3	3
all_values[4]	842829	1			T1	1		T2	2		T3	3
all_values[5]	842829	1			T1	1		T2	2		T3	3
all_values[6]	842829	1			T1	1		T2	2		T3	3
all_values[7]	842829	1			T1	1		T2	2		T3	3
all_values[8]	842829	1			T1	1		T2	2		T3	3
all_values[9]	842829	1			T1	1		T2	2		T3	3
all_values[10]	842829	1			T1	1		T2	2		T3	3
all_values[11]	842829	1			T1	1		T2	2		T3	3
all_values[12]	842829	1			T1	1		T2	2		T3	3
all_values[13]	842829	1			T1	1		T2	2		T3	3
all_values[14]	842829	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10369116

1

T1

15

T2

30

T3

40

auto[1]

2273319

1

T3

5

T4

26

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10823184

1

T1

15

T2

30

T3

45

auto[1]

1819251

1

T122

67025

T199

107792

T78

62

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98977	1			T1	1		T2	2		T3	1
all_values[0]	auto[0]	auto[1]	15896	1			T122	395		T199	67		T78	3
all_values[0]	auto[1]	auto[0]	616442	1			T3	2		T4	13		T6	2
all_values[0]	auto[1]	auto[1]	111514	1			T122	4074		T199	7120		T78	1
all_values[1]	auto[0]	auto[0]	715010	1			T1	1		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	127072	1			T122	4441		T199	7183		T78	5
all_values[1]	auto[1]	auto[0]	420	1			T40	1		T196	1		T180	14
all_values[1]	auto[1]	auto[1]	327	1			T122	26		T199	4		T78	1
all_values[2]	auto[0]	auto[0]	715225	1			T1	1		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	127273	1			T122	4460		T199	7185		T78	4
all_values[2]	auto[1]	auto[0]	191	1			T45	1		T76	2		T62	1
all_values[2]	auto[1]	auto[1]	140	1			T122	9		T199	2		T78	2
all_values[3]	auto[0]	auto[0]	745991	1			T1	1		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	96675	1			T122	4463		T199	7185		T78	2
all_values[3]	auto[1]	auto[1]	163	1			T122	6		T199	2		T78	3
all_values[4]	auto[0]	auto[0]	715421	1			T1	1		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	127247	1			T122	4461		T199	7183		T240	4
all_values[4]	auto[1]	auto[0]	20	1			T12	2		T13	1		T249	2
all_values[4]	auto[1]	auto[1]	141	1			T122	7		T199	2		T240	5
all_values[5]	auto[0]	auto[0]	745994	1			T1	1		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	96658	1			T122	4458		T199	7182		T78	3
all_values[5]	auto[1]	auto[1]	177	1			T122	10		T199	5		T78	3
all_values[6]	auto[0]	auto[0]	715425	1			T1	1		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	127219	1			T122	4454		T199	7182		T78	4
all_values[6]	auto[1]	auto[1]	185	1			T122	15		T199	5		T78	2
all_values[7]	auto[0]	auto[0]	686436	1			T1	1		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	124506	1			T122	4254		T199	6948		T78	4
all_values[7]	auto[1]	auto[0]	29005	1			T29	1		T43	1		T11	9
all_values[7]	auto[1]	auto[1]	2882	1			T122	215		T199	238		T78	2
all_values[8]	auto[0]	auto[0]	715441	1			T1	1		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	127202	1			T122	4460		T199	7181		T78	2
all_values[8]	auto[1]	auto[1]	186	1			T122	7		T199	3		T78	4
all_values[9]	auto[0]	auto[0]	164395	1			T1	1		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	7691	1			T122	340		T199	286		T240	9
all_values[9]	auto[1]	auto[0]	581611	1			T3	1		T9	1		T45	1
all_values[9]	auto[1]	auto[1]	89132	1			T122	4129		T199	6900		T20	6428
all_values[10]	auto[0]	auto[0]	715441	1			T1	1		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	127234	1			T122	4460		T199	7181		T240	4
all_values[10]	auto[1]	auto[1]	154	1			T122	9		T199	4		T240	3
all_values[11]	auto[0]	auto[0]	2409	1			T1	1		T2	2		T3	1
all_values[11]	auto[0]	auto[1]	353	1			T122	29		T199	13		T78	4
all_values[11]	auto[1]	auto[0]	713022	1			T3	2		T4	13		T6	2
all_values[11]	auto[1]	auto[1]	127045	1			T122	4440		T199	7171		T78	1
all_values[12]	auto[0]	auto[0]	715364	1			T1	1		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	127253	1			T122	4462		T199	7182		T78	4
all_values[12]	auto[1]	auto[0]	66	1			T45	1		T62	1		T47	1
all_values[12]	auto[1]	auto[1]	146	1			T122	6		T199	5		T78	2
all_values[13]	auto[0]	auto[0]	715447	1			T1	1		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	127207	1			T122	4457		T199	7185		T240	5
all_values[13]	auto[1]	auto[1]	175	1			T122	10		T199	2		T240	3
all_values[14]	auto[0]	auto[0]	715431	1			T1	1		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	127223	1			T122	4463		T199	7181		T78	5
all_values[14]	auto[1]	auto[1]	175	1			T122	5		T199	5		T78	1