---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.i2c_core.u_fifos.AcqWriteStableBeforeHandshake_A	0	0	387565049	0	0	0
tb.dut.i2c_core.u_fifos.FmtWriteStableBeforeHandshake_A	0	0	390033414	0	0	0
tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A	0	0	390033414	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.LockArbDecision_A	0	0	390033414	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.NoReadyValidNoGrant_A	0	0	390033414	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqStaysHighUntilGranted0_M	0	0	390033414	0	0	0
tb.dut.i2c_csr_assert.TlulOOBAddrErr_A	0	0	390750892	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	390033414	389859396	0	0
tb.dut.CioSclEnKnownO_A	0	0	390033414	389859396	0	0
tb.dut.CioSclKnownO_A	0	0	390033414	389859396	0	0
tb.dut.CioSdaEnKnownO_A	0	0	390033414	389859396	0	0
tb.dut.CioSdaKnownO_A	0	0	390033414	389859396	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	390033414	60	0	0
tb.dut.IntrAcqStretchKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrAcqWtmkKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrCommandCompleteKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrControllerHaltKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrFmtWtmkKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrHostTimeoutKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrRxOflwKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrRxWtmkKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrSclInterfKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrSdaInterfKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrSdaUnstableKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrStretchTimeoutKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrTxStretchKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrTxWtmkKnownO_A	0	0	390033414	389859396	0	0
tb.dut.IntrUnexpStopKnownO_A	0	0	390033414	389859396	0	0
tb.dut.TlAReadyKnownO_A	0	0	390033414	389859396	0	0
tb.dut.TlDValidKnownO_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.AcqFifoDepthValid_A	0	0	1692	1692	0	0
tb.dut.i2c_core.FifoDepthValid_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_acq_overflow.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_acq_threshold.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_cmd_complete.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_controller_halt.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_fmt_threshold.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_host_timeout.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_rx_overflow.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_rx_threshold.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_scl_interference.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_sda_interference.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_sda_unstable.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_stretch_timeout.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_tx_stretch.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_tx_threshold.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.intr_hw_unexp_stop.IntrTKind_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.RamDepthSuffices_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.RamWidthSuffices_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.MinimalSramAw_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoErr_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	390033414	170996024	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	390033414	59856	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	390033414	239522	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	390033414	239522	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	390033414	318196	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	318196	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	390033414	230519480	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	230519480	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.MinimalSramAw_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoErr_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	390033414	329947580	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	390033414	22819408	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	390033414	168590	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	390033414	168590	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	390033414	193299	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	193299	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	390033414	119463987	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	119463987	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.CannotHaveEccAndParity_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	390033414	675559	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.CheckHotOne_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.CheckNGreaterZero_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GntImpliesReady_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GntImpliesValid_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GrantKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.IdxKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.IndexIsCorrect_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReadyAndValidImplyGrant_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqAndReadyImplyGrant_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqImpliesValid_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A	0	0	390033414	68	0	1692
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ValidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.gen_data_port_assertion.DataFlow_A	0	0	390033414	1313677	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.MinimalSramAw_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoErr_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	390033414	365820846	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	390033414	236949	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	390033414	119412	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	390033414	119412	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	390033414	205288	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	205288	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	390033414	26309301	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	26309301	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.MinimalSramAw_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1692	1692	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoErr_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	390033414	369073689	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	390033414	330338	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	390033414	110594	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	390033414	110594	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	390033414	159993	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	159993	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	390033414	33016605	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.DataKnown_AKnownEnable	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390033414	33016605	0	0
tb.dut.i2c_core.u_i2c_controller_fsm.SclOutputGlitch_A	0	0	390033414	3479573	0	0
tb.dut.i2c_core.u_i2c_target_fsm.AcqDepthRdCheck_A	0	0	390033414	993693	0	0
tb.dut.i2c_core.u_i2c_target_fsm.AcqFifoDeepEnough_A	0	0	390033414	389859396	0	0
tb.dut.i2c_core.u_i2c_target_fsm.SclOutputGlitch_A	0	0	390033414	60921	0	0
tb.dut.i2c_csr_assert.ctrl_rd_A	0	0	390750892	2643	0	0
tb.dut.i2c_csr_assert.host_fifo_config_rd_A	0	0	390750892	5610	0	0
tb.dut.i2c_csr_assert.host_nack_handler_timeout_rd_A	0	0	390750892	1818	0	0
tb.dut.i2c_csr_assert.host_timeout_ctrl_rd_A	0	0	390750892	1778	0	0
tb.dut.i2c_csr_assert.intr_enable_rd_A	0	0	390750892	4353	0	0
tb.dut.i2c_csr_assert.ovrd_rd_A	0	0	390750892	1958	0	0
tb.dut.i2c_csr_assert.target_fifo_config_rd_A	0	0	390750892	1973	0	0
tb.dut.i2c_csr_assert.target_id_rd_A	0	0	390750892	2299	0	0
tb.dut.i2c_csr_assert.target_timeout_ctrl_rd_A	0	0	390750892	1907	0	0
tb.dut.i2c_csr_assert.timeout_ctrl_rd_A	0	0	390750892	2331	0	0
tb.dut.i2c_csr_assert.timing0_rd_A	0	0	390750892	2046	0	0
tb.dut.i2c_csr_assert.timing1_rd_A	0	0	390750892	2037	0	0
tb.dut.i2c_csr_assert.timing2_rd_A	0	0	390750892	1893	0	0
tb.dut.i2c_csr_assert.timing3_rd_A	0	0	390750892	1796	0	0
tb.dut.i2c_csr_assert.timing4_rd_A	0	0	390750892	2006	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	390750892	40285077	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	390750892	390542129	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	390750892	390542129	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	390750892	49030501	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	390750892	390542129	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	390750892	390542129	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
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tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1857	1857	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	390752050	1188735	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	390750892	3449	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	390752050	39635557	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	390752050	47401539	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	390750892	3385	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	390752050	40285159	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	390752050	49030604	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	390752050	40285159	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	390752050	49030604	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	390752050	49030604	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	390752050	49030604	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	390750892	3163	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	390750892	3412	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1857	1857	0	0
tb.dut.u_reg.en2addrHit	0	0	390750892	36644423	0	0
tb.dut.u_reg.reAfterRv	0	0	390750892	36644310	0	0
tb.dut.u_reg.rePulse	0	0	390750892	35858203	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1857	1857	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1857	1857	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1857	1857	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1857	1857	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1857	1857	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1857	1857	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1857	1857	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1857	1857	0	0
tb.dut.u_reg.wePulse	0	0	390750892	786107	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A	0	0	390033414	68	0	1692

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	390752050	201473	201473	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	390752050	191	191	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	390752050	206	206	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	390752050	126	126	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	390752050	24	24	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	390752050	106	106	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	390752050	133	133	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	390752050	3534	3534	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	390752050	2698064	2698064	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	390752050	18834750	18834750	1837

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	390752050	201473	201473	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	390752050	191	191	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	390752050	206	206	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	390752050	126	126	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	390752050	24	24	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	390752050	106	106	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	390752050	133	133	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	390752050	3534	3534	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	390752050	2698064	2698064	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	390752050	18834750	18834750	1837