Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	842829	1			T1	1		T2	2		T3	3
all_pins[1]	842829	1			T1	1		T2	2		T3	3
all_pins[2]	842829	1			T1	1		T2	2		T3	3
all_pins[3]	842829	1			T1	1		T2	2		T3	3
all_pins[4]	842829	1			T1	1		T2	2		T3	3
all_pins[5]	842829	1			T1	1		T2	2		T3	3
all_pins[6]	842829	1			T1	1		T2	2		T3	3
all_pins[7]	842829	1			T1	1		T2	2		T3	3
all_pins[8]	842829	1			T1	1		T2	2		T3	3
all_pins[9]	842829	1			T1	1		T2	2		T3	3
all_pins[10]	842829	1			T1	1		T2	2		T3	3
all_pins[11]	842829	1			T1	1		T2	2		T3	3
all_pins[12]	842829	1			T1	1		T2	2		T3	3
all_pins[13]	842829	1			T1	1		T2	2		T3	3
all_pins[14]	842829	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10374646	1			T1	15		T2	30		T3	40
values[0x1]	2267789	1			T3	5		T4	26		T6	4
transitions[0x0=>0x1]	2266762	1			T3	5		T4	26		T6	4
transitions[0x1=>0x0]	2265446	1			T3	4		T4	25		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118421	1			T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	724408	1			T3	2		T4	13		T6	2
all_pins[0]	transitions[0x0=>0x1]	723672	1			T3	2		T4	13		T6	2
all_pins[0]	transitions[0x1=>0x0]	59	1			T122	4		T199	1		T78	1
all_pins[1]	values[0x0]	842034	1			T1	1		T2	2		T3	3
all_pins[1]	values[0x1]	795	1			T40	2		T196	2		T180	16
all_pins[1]	transitions[0x0=>0x1]	778	1			T40	2		T196	2		T180	16
all_pins[1]	transitions[0x1=>0x0]	106	1			T45	1		T271	1		T272	1
all_pins[2]	values[0x0]	842706	1			T1	1		T2	2		T3	3
all_pins[2]	values[0x1]	123	1			T45	1		T271	1		T272	1
all_pins[2]	transitions[0x0=>0x1]	109	1			T45	1		T271	1		T272	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T122	3		T78	2		T273	4
all_pins[3]	values[0x0]	842747	1			T1	1		T2	2		T3	3
all_pins[3]	values[0x1]	82	1			T122	4		T78	3		T274	1
all_pins[3]	transitions[0x0=>0x1]	67	1			T122	3		T78	3		T274	1
all_pins[3]	transitions[0x1=>0x0]	75	1			T12	2		T13	1		T249	2
all_pins[4]	values[0x0]	842739	1			T1	1		T2	2		T3	3
all_pins[4]	values[0x1]	90	1			T12	2		T13	1		T249	2
all_pins[4]	transitions[0x0=>0x1]	70	1			T12	2		T13	1		T249	2
all_pins[4]	transitions[0x1=>0x0]	72	1			T122	5		T199	1		T78	2
all_pins[5]	values[0x0]	842737	1			T1	1		T2	2		T3	3
all_pins[5]	values[0x1]	92	1			T122	5		T199	2		T78	2
all_pins[5]	transitions[0x0=>0x1]	63	1			T122	2		T199	2		T78	2
all_pins[5]	transitions[0x1=>0x0]	59	1			T122	4		T199	2		T240	1
all_pins[6]	values[0x0]	842741	1			T1	1		T2	2		T3	3
all_pins[6]	values[0x1]	88	1			T122	7		T199	2		T240	1
all_pins[6]	transitions[0x0=>0x1]	74	1			T122	6		T199	2		T240	1
all_pins[6]	transitions[0x1=>0x0]	34774	1			T29	1		T43	1		T41	1
all_pins[7]	values[0x0]	808041	1			T1	1		T2	2		T3	3
all_pins[7]	values[0x1]	34788	1			T29	1		T43	1		T41	1
all_pins[7]	transitions[0x0=>0x1]	34778	1			T29	1		T43	1		T41	1
all_pins[7]	transitions[0x1=>0x0]	81	1			T122	4		T199	2		T274	2
all_pins[8]	values[0x0]	842738	1			T1	1		T2	2		T3	3
all_pins[8]	values[0x1]	91	1			T122	4		T199	2		T78	1
all_pins[8]	transitions[0x0=>0x1]	59	1			T122	4		T199	2		T78	1
all_pins[8]	transitions[0x1=>0x0]	670660	1			T3	1		T9	1		T45	1
all_pins[9]	values[0x0]	172137	1			T1	1		T2	2		T3	2
all_pins[9]	values[0x1]	670692	1			T3	1		T9	1		T45	1
all_pins[9]	transitions[0x0=>0x1]	670671	1			T3	1		T9	1		T45	1
all_pins[9]	transitions[0x1=>0x0]	65	1			T122	3		T199	3		T240	1
all_pins[10]	values[0x0]	842743	1			T1	1		T2	2		T3	3
all_pins[10]	values[0x1]	86	1			T122	4		T199	3		T240	1
all_pins[10]	transitions[0x0=>0x1]	70	1			T122	4		T199	2		T240	1
all_pins[10]	transitions[0x1=>0x0]	836124	1			T3	2		T4	13		T6	2
all_pins[11]	values[0x0]	6689	1			T1	1		T2	2		T3	1
all_pins[11]	values[0x1]	836140	1			T3	2		T4	13		T6	2
all_pins[11]	transitions[0x0=>0x1]	836106	1			T3	2		T4	13		T6	2
all_pins[11]	transitions[0x1=>0x0]	102	1			T62	1		T47	1		T66	1
all_pins[12]	values[0x0]	842693	1			T1	1		T2	2		T3	3
all_pins[12]	values[0x1]	136	1			T45	1		T62	1		T47	1
all_pins[12]	transitions[0x0=>0x1]	120	1			T45	1		T62	1		T47	1
all_pins[12]	transitions[0x1=>0x0]	74	1			T122	4		T199	1		T240	1
all_pins[13]	values[0x0]	842739	1			T1	1		T2	2		T3	3
all_pins[13]	values[0x1]	90	1			T122	5		T199	2		T240	1
all_pins[13]	transitions[0x0=>0x1]	65	1			T122	5		T199	1		T240	1
all_pins[13]	transitions[0x1=>0x0]	63	1			T122	1		T199	1		T240	3
all_pins[14]	values[0x0]	842741	1			T1	1		T2	2		T3	3
all_pins[14]	values[0x1]	88	1			T122	1		T199	2		T240	3
all_pins[14]	transitions[0x0=>0x1]	60	1			T122	1		T199	2		T240	2
all_pins[14]	transitions[0x1=>0x0]	723064	1			T3	1		T4	12		T6	1