Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	365	1			T122	18		T199	7		T78	4
all_values[1]	365	1			T122	18		T199	7		T78	4
all_values[2]	365	1			T122	18		T199	7		T78	4
all_values[3]	365	1			T122	18		T199	7		T78	4
all_values[4]	365	1			T122	18		T199	7		T78	4
all_values[5]	365	1			T122	18		T199	7		T78	4
all_values[6]	365	1			T122	18		T199	7		T78	4
all_values[7]	365	1			T122	18		T199	7		T78	4
all_values[8]	365	1			T122	18		T199	7		T78	4
all_values[9]	365	1			T122	18		T199	7		T78	4
all_values[10]	365	1			T122	18		T199	7		T78	4
all_values[11]	365	1			T122	18		T199	7		T78	4
all_values[12]	365	1			T122	18		T199	7		T78	4
all_values[13]	365	1			T122	18		T199	7		T78	4
all_values[14]	365	1			T122	18		T199	7		T78	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2977

1

T122

159

T199

60

T78

30

auto[1]

2498

1

T122

111

T199

45

T78

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910

1

T122

10

T199

13

T78

20

auto[1]

4565

1

T122

260

T199

92

T78

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3246

1

T122

160

T199

61

T78

42

auto[1]

2229

1

T122

110

T199

44

T78

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T78	1		T240	1		T21	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T122	8		T78	1		T240	1
all_values[0]	auto[0]	auto[1]	auto[0]	13	1			T78	1		T275	2		T276	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T122	5		T199	4		T240	2
all_values[0]	auto[1]	auto[0]	auto[1]	97	1			T122	4		T199	2		T240	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1			T122	1		T199	1		T78	1
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T20	1		T274	2		T273	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T122	5		T199	1		T240	1
all_values[1]	auto[0]	auto[1]	auto[0]	18	1			T122	2		T273	1		T277	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T122	3		T199	2		T78	3
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T122	2		T199	3		T78	1
all_values[1]	auto[1]	auto[1]	auto[1]	76	1			T122	6		T199	1		T274	1
all_values[2]	auto[0]	auto[0]	auto[0]	26	1			T20	1		T278	1		T136	1
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T122	6		T199	4		T78	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1			T20	1		T136	1		T279	2
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T122	3		T199	1		T78	1
all_values[2]	auto[1]	auto[0]	auto[1]	75	1			T122	5		T199	1		T78	1
all_values[2]	auto[1]	auto[1]	auto[1]	65	1			T122	4		T199	1		T78	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T78	1		T240	2		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T122	5		T199	4		T240	2
all_values[3]	auto[0]	auto[1]	auto[0]	27	1			T273	1		T280	2		T278	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T122	8		T78	1		T240	1
all_values[3]	auto[1]	auto[0]	auto[1]	81	1			T122	3		T199	3		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	64	1			T122	2		T78	2		T240	2
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T122	1		T199	2		T78	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T122	7		T199	3		T240	1
all_values[4]	auto[0]	auto[1]	auto[0]	25	1			T78	3		T274	2		T275	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T122	3		T240	1		T274	1
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T122	6		T199	1		T240	2
all_values[4]	auto[1]	auto[1]	auto[1]	60	1			T122	1		T199	1		T240	3
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T122	1		T280	2		T278	1
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T122	3		T199	2		T240	2
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T274	1		T280	2		T278	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T122	5		T199	3		T78	2
all_values[5]	auto[1]	auto[0]	auto[1]	89	1			T122	8		T199	2		T78	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1			T122	1		T78	1		T274	2
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T20	1		T135	2		T136	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T122	5		T199	2		T78	3
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T135	2		T281	1		T276	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T122	2		T199	1		T240	1
all_values[6]	auto[1]	auto[0]	auto[1]	93	1			T122	5		T199	3		T78	1
all_values[6]	auto[1]	auto[1]	auto[1]	64	1			T122	6		T199	1		T240	2
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T199	1		T20	1		T274	2
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T122	7		T199	2		T240	1
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T278	1		T282	3		T283	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T122	3		T199	2		T78	2
all_values[7]	auto[1]	auto[0]	auto[1]	75	1			T122	5		T199	2		T78	1
all_values[7]	auto[1]	auto[1]	auto[1]	53	1			T122	3		T78	1		T240	1
all_values[8]	auto[0]	auto[0]	auto[0]	41	1			T199	2		T20	1		T135	1
all_values[8]	auto[0]	auto[0]	auto[1]	67	1			T122	4		T199	1		T78	1
all_values[8]	auto[0]	auto[1]	auto[0]	24	1			T122	2		T199	1		T20	1
all_values[8]	auto[0]	auto[1]	auto[1]	71	1			T122	5		T199	1		T240	1
all_values[8]	auto[1]	auto[0]	auto[1]	91	1			T122	6		T199	1		T78	1
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T122	1		T199	1		T78	2
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T199	1		T78	1		T20	1
all_values[9]	auto[0]	auto[0]	auto[1]	65	1			T122	9		T199	2		T240	2
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T78	3		T273	1		T280	4
all_values[9]	auto[0]	auto[1]	auto[1]	72	1			T122	3		T199	2		T240	4
all_values[9]	auto[1]	auto[0]	auto[1]	70	1			T122	3		T199	1		T240	1
all_values[9]	auto[1]	auto[1]	auto[1]	84	1			T122	3		T199	1		T20	2
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T199	2		T78	1		T240	2
all_values[10]	auto[0]	auto[0]	auto[1]	69	1			T122	4		T240	2		T20	1
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T78	3		T274	2		T284	3
all_values[10]	auto[0]	auto[1]	auto[1]	75	1			T122	5		T199	1		T20	1
all_values[10]	auto[1]	auto[0]	auto[1]	81	1			T122	7		T240	1		T20	2
all_values[10]	auto[1]	auto[1]	auto[1]	73	1			T122	2		T199	4		T240	2
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T199	2		T78	1		T240	1
all_values[11]	auto[0]	auto[0]	auto[1]	79	1			T122	9		T78	1		T240	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T199	1		T21	3		T280	1
all_values[11]	auto[0]	auto[1]	auto[1]	87	1			T122	4		T199	3		T78	1
all_values[11]	auto[1]	auto[0]	auto[1]	87	1			T122	2		T78	1		T240	2
all_values[11]	auto[1]	auto[1]	auto[1]	54	1			T122	3		T199	1		T240	2
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T240	1		T20	1		T278	2
all_values[12]	auto[0]	auto[0]	auto[1]	90	1			T122	7		T78	2		T240	4
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T122	1		T273	1		T285	1
all_values[12]	auto[0]	auto[1]	auto[1]	71	1			T122	4		T199	2		T20	1
all_values[12]	auto[1]	auto[0]	auto[1]	89	1			T122	3		T199	4		T78	2
all_values[12]	auto[1]	auto[1]	auto[1]	57	1			T122	3		T199	1		T20	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T78	2		T240	1		T20	1
all_values[13]	auto[0]	auto[0]	auto[1]	72	1			T122	4		T240	2		T20	1
all_values[13]	auto[0]	auto[1]	auto[0]	34	1			T122	2		T78	2		T274	2
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T122	3		T199	4		T240	2
all_values[13]	auto[1]	auto[0]	auto[1]	66	1			T122	5		T199	1		T20	1
all_values[13]	auto[1]	auto[1]	auto[1]	80	1			T122	4		T199	2		T240	2
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T122	1		T199	1		T20	1
all_values[14]	auto[0]	auto[0]	auto[1]	80	1			T122	7		T199	1		T78	3
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T278	2		T286	1		T285	3
all_values[14]	auto[0]	auto[1]	auto[1]	72	1			T122	4		T240	2		T20	2
all_values[14]	auto[1]	auto[0]	auto[1]	83	1			T122	2		T199	3		T78	1
all_values[14]	auto[1]	auto[1]	auto[1]	72	1			T122	4		T199	2		T240	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal