Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30411760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7448040

1

T1

10

T2

22

T3

94

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37070928	1			T1	11		T2	57		T3	162
values[0x0]	393840	1			T1	8		T2	29		T3	52
values[0x1]	395032	1			T1	6		T2	25		T3	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21180201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16679599

1

T1

13

T2

52

T3

146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	125661	1			T3	2		T4	1		T8	17
valid_sources[0x01]	128630	1			T8	19		T9	47		T44	6
valid_sources[0x02]	136094	1			T3	1		T6	1		T8	22
valid_sources[0x03]	156698	1			T4	1		T8	21		T9	44
valid_sources[0x04]	149788	1			T3	1		T8	18		T9	50
valid_sources[0x05]	168410	1			T1	2		T2	7		T3	1
valid_sources[0x06]	138136	1			T2	2		T6	1		T8	23
valid_sources[0x07]	174376	1			T8	28		T9	54		T44	4
valid_sources[0x08]	157379	1			T6	1		T8	31		T9	27
valid_sources[0x09]	147908	1			T3	1		T8	20		T9	34
valid_sources[0x0a]	165515	1			T3	3		T6	1		T8	13
valid_sources[0x0b]	145435	1			T3	1		T6	1		T8	15
valid_sources[0x0c]	137864	1			T3	1		T8	17		T9	30
valid_sources[0x0d]	165196	1			T3	3		T8	21		T9	28
valid_sources[0x0e]	161271	1			T3	2		T8	16		T9	39
valid_sources[0x0f]	147794	1			T8	18		T9	40		T10	1
valid_sources[0x10]	140637	1			T3	2		T8	26		T9	27
valid_sources[0x11]	144388	1			T8	17		T9	44		T44	2
valid_sources[0x12]	140092	1			T3	2		T8	25		T9	38
valid_sources[0x13]	145011	1			T6	1		T8	24		T9	34
valid_sources[0x14]	141844	1			T6	5		T8	22		T9	37
valid_sources[0x15]	154310	1			T3	2		T8	23		T9	42
valid_sources[0x16]	139702	1			T3	1		T8	24		T9	32
valid_sources[0x17]	198841	1			T4	1		T8	27		T9	38
valid_sources[0x18]	154770	1			T2	1		T3	1		T8	30
valid_sources[0x19]	153411	1			T3	1		T8	27		T9	34
valid_sources[0x1a]	143900	1			T3	3		T8	26		T9	35
valid_sources[0x1b]	155833	1			T2	2		T8	21		T9	38
valid_sources[0x1c]	152693	1			T2	3		T3	3		T8	29
valid_sources[0x1d]	164572	1			T3	1		T8	18		T9	55
valid_sources[0x1e]	149432	1			T3	2		T6	3		T8	23
valid_sources[0x1f]	137703	1			T3	2		T4	1		T8	20
valid_sources[0x20]	149595	1			T6	1		T8	19		T9	29
valid_sources[0x21]	152354	1			T1	2		T8	24		T9	64
valid_sources[0x22]	149999	1			T3	2		T4	1		T5	4016
valid_sources[0x23]	134106	1			T3	1		T6	1		T8	11
valid_sources[0x24]	146834	1			T8	20		T9	35		T44	3
valid_sources[0x25]	137585	1			T3	2		T8	26		T9	46
valid_sources[0x26]	137883	1			T3	1		T8	16		T9	39
valid_sources[0x27]	146612	1			T3	1		T8	23		T9	48
valid_sources[0x28]	175492	1			T2	5		T3	3		T6	2
valid_sources[0x29]	141560	1			T8	28		T9	38		T10	2
valid_sources[0x2a]	140768	1			T1	3		T3	1		T8	20
valid_sources[0x2b]	143074	1			T3	2		T8	16		T9	36
valid_sources[0x2c]	140718	1			T6	2		T8	23		T9	29
valid_sources[0x2d]	143111	1			T3	1		T8	12		T9	39
valid_sources[0x2e]	141961	1			T3	2		T6	1		T8	21
valid_sources[0x2f]	155513	1			T2	3		T8	20		T9	51
valid_sources[0x30]	137237	1			T3	1		T8	18		T9	41
valid_sources[0x31]	150256	1			T2	7		T3	2		T4	1
valid_sources[0x32]	129690	1			T3	4		T8	23		T9	27
valid_sources[0x33]	151266	1			T3	2		T4	1		T8	11
valid_sources[0x34]	144940	1			T3	1		T8	20		T9	42
valid_sources[0x35]	167926	1			T2	1		T3	2		T8	16
valid_sources[0x36]	140860	1			T8	31		T9	50		T10	3
valid_sources[0x37]	139432	1			T6	1		T8	41		T9	56
valid_sources[0x38]	139653	1			T3	1		T8	34		T9	40
valid_sources[0x39]	176144	1			T3	1		T8	23		T9	61
valid_sources[0x3a]	132528	1			T8	22		T9	41		T10	3
valid_sources[0x3b]	177281	1			T3	2		T6	1		T8	24
valid_sources[0x3c]	139431	1			T3	3		T8	25		T9	36
valid_sources[0x3d]	168832	1			T2	1		T3	1		T8	26
valid_sources[0x3e]	150404	1			T2	2		T8	21		T9	22
valid_sources[0x3f]	143619	1			T2	1		T3	3		T5	1
valid_sources[0x40]	144120	1			T3	1		T8	11		T9	34
valid_sources[0x41]	149337	1			T2	1		T8	10		T9	44
valid_sources[0x42]	147147	1			T3	2		T6	4		T8	25
valid_sources[0x43]	131227	1			T6	1		T8	20		T9	34
valid_sources[0x44]	136974	1			T3	1		T8	42		T9	57
valid_sources[0x45]	137668	1			T1	2		T3	1		T8	23
valid_sources[0x46]	165723	1			T3	1		T4	1		T8	16
valid_sources[0x47]	145030	1			T3	3		T6	2		T8	22
valid_sources[0x48]	150264	1			T8	20		T9	33		T10	4
valid_sources[0x49]	154373	1			T3	2		T8	24		T9	50
valid_sources[0x4a]	159609	1			T3	2		T8	22		T9	28
valid_sources[0x4b]	158264	1			T2	1		T8	23		T9	28
valid_sources[0x4c]	144050	1			T3	1		T8	24		T9	45
valid_sources[0x4d]	145051	1			T8	15		T9	39		T10	4
valid_sources[0x4e]	133558	1			T3	2		T6	2		T8	28
valid_sources[0x4f]	158115	1			T2	3		T3	4		T5	1
valid_sources[0x50]	148596	1			T2	1		T3	2		T6	1
valid_sources[0x51]	133710	1			T3	3		T6	2		T8	12
valid_sources[0x52]	133429	1			T8	19		T9	48		T10	2
valid_sources[0x53]	166588	1			T3	3		T8	30		T9	51
valid_sources[0x54]	173386	1			T8	19		T9	29		T44	2
valid_sources[0x55]	141452	1			T1	3		T6	1		T8	17
valid_sources[0x56]	140825	1			T8	21		T9	34		T44	4
valid_sources[0x57]	134196	1			T1	1		T8	27		T9	32
valid_sources[0x58]	141617	1			T3	2		T8	22		T9	48
valid_sources[0x59]	150485	1			T3	1		T8	22		T9	29
valid_sources[0x5a]	158423	1			T3	1		T8	14		T9	42
valid_sources[0x5b]	168751	1			T4	1		T8	12		T9	74
valid_sources[0x5c]	142534	1			T2	2		T3	1		T8	29
valid_sources[0x5d]	145445	1			T3	2		T4	1		T8	21
valid_sources[0x5e]	148169	1			T6	1		T8	22		T9	38
valid_sources[0x5f]	136923	1			T3	3		T8	36		T9	41
valid_sources[0x60]	141647	1			T3	2		T8	32		T9	47
valid_sources[0x61]	138631	1			T6	1		T8	25		T9	36
valid_sources[0x62]	144107	1			T2	1		T3	2		T8	19
valid_sources[0x63]	187456	1			T3	1		T8	26		T9	50
valid_sources[0x64]	142745	1			T8	24		T9	32		T44	6
valid_sources[0x65]	142225	1			T3	1		T8	34		T9	50
valid_sources[0x66]	148616	1			T4	1		T8	25		T9	42
valid_sources[0x67]	159179	1			T3	2		T4	1		T6	1
valid_sources[0x68]	144702	1			T4	1		T8	26		T9	52
valid_sources[0x69]	149671	1			T8	30		T9	46		T10	9
valid_sources[0x6a]	132803	1			T3	1		T8	18		T9	50
valid_sources[0x6b]	140339	1			T3	2		T8	17		T9	38
valid_sources[0x6c]	148869	1			T3	1		T6	1		T8	16
valid_sources[0x6d]	145002	1			T8	21		T9	47		T44	4
valid_sources[0x6e]	145378	1			T3	1		T8	22		T9	39
valid_sources[0x6f]	151310	1			T6	2		T8	21		T9	43
valid_sources[0x70]	137478	1			T3	3		T6	1		T8	22
valid_sources[0x71]	138483	1			T3	1		T4	1		T8	19
valid_sources[0x72]	141983	1			T8	24		T9	20		T10	1
valid_sources[0x73]	145272	1			T3	1		T4	1		T8	17
valid_sources[0x74]	147280	1			T2	1		T3	1		T6	1
valid_sources[0x75]	142635	1			T3	3		T8	30		T9	48
valid_sources[0x76]	145278	1			T8	24		T9	29		T10	2
valid_sources[0x77]	153863	1			T3	1		T8	14		T9	35
valid_sources[0x78]	138890	1			T3	1		T8	25		T9	43
valid_sources[0x79]	142895	1			T8	22		T9	42		T10	9
valid_sources[0x7a]	164221	1			T6	1		T8	19		T9	30
valid_sources[0x7b]	138234	1			T2	1		T3	1		T6	1
valid_sources[0x7c]	146212	1			T2	1		T3	2		T8	21
valid_sources[0x7d]	187867	1			T8	26		T9	37		T10	4
valid_sources[0x7e]	154231	1			T3	1		T8	29		T9	53
valid_sources[0x7f]	137582	1			T2	3		T8	26		T9	49
valid_sources[0x80]	163644	1			T3	1		T8	20		T9	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7096800

1

T1

5

T2

1

T3

19

values[0x0]

all_enables

biggest_size

207785

1

T1

4

T2

18

T3

42

values[0x1]

all_enables

biggest_size

143455

1

T1

1

T2

3

T3

33