Module Definition
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Module : prim_fifo_sync_cnt
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 88.21 100.00 80.00 84.62
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.21 100.00 80.00 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.21 100.00 80.00 84.62


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 66.67 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.63 100.00 74.51 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.63 100.00 74.51 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
88.21 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T2 T3 T5 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T5 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T2 T3 T5 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T5 
133                           end
                        MISSING_ELSE
Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T8 T44 T23 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T5 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T8 T44 T23 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T8 T9 
133                           end
                        MISSING_ELSE
Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T47 T74 T76 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T44 T47 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T47 T74 T76 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T44 T47 
133                           end
                        MISSING_ELSE
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT47,T74,T76
10CoveredT5,T44,T47
11CoveredT47,T74,T76 

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT47,T74,T76 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT47,T74,T76
10CoveredT5,T44,T47
11CoveredT47,T74,T76 

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT47,T74,T76 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT63,T50,T64 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT63,T50,T64 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT47,T74,T76
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT47,T74,T76
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
88.21 80.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T5
11CoveredT2,T3,T5 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T5
11CoveredT2,T3,T5 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T44,T23
10CoveredT2,T3,T5
11CoveredT8,T44,T23 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T44,T23 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T44,T23
10CoveredT5,T8,T9
11CoveredT8,T44,T23 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T44,T23 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T42,T149 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T42,T149 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T44,T23
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T44,T23
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T8
0 1 Covered T1,T2,T3
0 0 Covered T8,T9,T10 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T8
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T8
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T9 T10 T11 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T9 T10 T11 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T9 T10 T11 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T9 T10 T11 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT9,T10,T11
11CoveredT9,T10,T11 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT9,T10,T11
11CoveredT9,T10,T11 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 11 84.62
TERNARY 68 3 1 33.33
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T10,T11
0 0 0 1 Covered T9,T10,T11
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T10,T11
0 0 0 1 Covered T9,T10,T11
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T2 T3 T8 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T8 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T2 T3 T8 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T8 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT2,T3,T8
11CoveredT2,T3,T8 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT2,T3,T8
11CoveredT2,T3,T8 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT23,T181,T183
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT23,T181,T183
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T23,T181,T183 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T8
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T8
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT74,T46,T170
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT74,T46,T170
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T74,T46,T170 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT83,T216,T217
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT83,T216,T217
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T83,T216,T217 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T2 T3 T8 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T8 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T8 T9 T10 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T8 T9 T10 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT2,T3,T8
11CoveredT2,T3,T8 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT8,T9,T10
11CoveredT8,T9,T10 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T10 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T8
0 1 Covered T1,T2,T3
0 0 Covered T8,T9,T10 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T8
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T10
0 0 0 1 Covered T8,T9,T10
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T8 T23 T42 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T8 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T8 T23 T42 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T8 T9 T10 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T23,T42
10CoveredT2,T3,T8
11CoveredT8,T23,T42 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T23,T42 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T23,T42
10CoveredT8,T9,T10
11CoveredT8,T23,T42 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T23,T42 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T42,T149 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T42,T149 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T23,T42
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T23,T42
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T8,T42,T149
0 1 Covered T1,T2,T3
0 0 Covered T8,T23,T42 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T23,T42
0 0 0 1 Covered T2,T3,T8
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T23,T42
0 0 0 1 Covered T8,T9,T10
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T9 T10 T11 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T9 T10 T11 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T9 T10 T11 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T9 T10 T11 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT9,T10,T11
11CoveredT9,T10,T11 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT9,T10,T11
11CoveredT9,T10,T11 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T11
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T11
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T79,T80,T81
0 1 Covered T1,T2,T3
0 0 Covered T9,T10,T11 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T10,T11
0 0 0 1 Covered T9,T10,T11
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T10,T11
0 0 0 1 Covered T9,T10,T11
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T79 T80 T81 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T79 T80 T81 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T79 T80 T81 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T79 T80 T81 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT79,T80,T81
10CoveredT79,T80,T81
11CoveredT79,T80,T81 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT79,T80,T81
10CoveredT79,T80,T81
11CoveredT79,T80,T81 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T80,T81 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT79,T80,T81
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT79,T80,T81
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T79,T80,T81
0 1 Covered T1,T2,T3
0 0 Covered T79,T80,T81 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T79,T80,T81
0 0 0 1 Covered T79,T80,T81
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T79,T80,T81
0 0 0 1 Covered T79,T80,T81
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T1,T2,T3
0 0 Covered T5,T6,T7 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T44 T47 T74 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T44 T47 T74 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT44,T47,T74
10CoveredT5,T6,T7
11CoveredT44,T47,T74 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT44,T47,T74 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT44,T47,T74
10CoveredT5,T6,T7
11CoveredT44,T47,T74 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT44,T47,T74 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT60,T61,T62 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT60,T61,T62 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT44,T47,T74
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT44,T47,T74
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T60,T61,T62
0 1 Covered T1,T2,T3
0 0 Covered T44,T47,T74 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T44,T47,T74
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T44,T47,T74
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T5 T6 T7 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T5 T6 T44 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T6 T7 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T44 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T44 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T44 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T44
0 1 Covered T1,T2,T3
0 0 Covered T5,T6,T7 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T7
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T6,T44
0 0 0 1 Covered T5,T6,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T47 T74 T76 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T44 T47 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T47 T74 T76 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T5 T44 T47 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT47,T74,T76
10CoveredT5,T44,T47
11CoveredT47,T74,T76 

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT47,T74,T76 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT47,T74,T76
10CoveredT5,T44,T47
11CoveredT47,T74,T76 

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT47,T74,T76 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT63,T50,T64 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT63,T50,T64 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT47,T74,T76
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT47,T74,T76
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T63,T50,T64
0 1 Covered T1,T2,T3
0 0 Covered T47,T74,T76 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T47,T74,T76
0 0 0 1 Covered T5,T44,T47
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T47,T74,T76
0 0 0 1 Covered T5,T44,T47
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%