Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T2 T3
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=13,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=30,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Line Coverage for Module :
prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 168 | 0 | 0 | |
139 // WARN: we signal is actually read signal not write enable.
140 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
141 if (Mubi) begin : gen_mubi
142 if (DW == 4) begin : gen_mubi4
143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
144 (we ? prim_mubi_pkg::MuBi4False :
145 prim_mubi_pkg::MuBi4True));
146 end else if (DW == 8) begin : gen_mubi8
147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
148 (we ? prim_mubi_pkg::MuBi8False :
149 prim_mubi_pkg::MuBi8True));
150 end else if (DW == 12) begin : gen_mubi12
151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
152 (we ? prim_mubi_pkg::MuBi12False :
153 prim_mubi_pkg::MuBi12True));
154 end else if (DW == 16) begin : gen_mubi16
155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
156 (we ? prim_mubi_pkg::mubi16_t'(wd) :
157 prim_mubi_pkg::MuBi16True));
158 end else begin : gen_invalid_mubi
159 $error("%m: Invalid width for MuBi");
160 end
161 end else begin : gen_non_mubi
162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1);
Tests: T1 T2 T3
163 end
164 // Unused wd - Prevent lint errors.
165 logic [DW-1:0] unused_wd;
166 //VCS coverage off
167 // pragma coverage off
168 unreachable assign unused_wd = wd;
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 3 | 3 | 100.00 |
| Logical | 3 | 3 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 140
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T63,T64,T60 |
| 1 | 0 | Covered | T63,T64,T60 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T5,T6 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T5,T6 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T17,T80 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T80,T32,T101 |
| 1 | 1 | Covered | T3,T17,T80 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T17,T80 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=13,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T5,T6 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T11,T63,T64 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T63,T64 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T63,T64 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T6,T7 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=20,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T6,T7 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T3,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T5,T6 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=30,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T5,T6 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
Branch Coverage for Module :
prim_subreg_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |