Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	399229137	0	0	0
ctrl_rd_A	399229137	2865	0	0
host_fifo_config_rd_A	399229137	4083	0	0
host_nack_handler_timeout_rd_A	399229137	1659	0	0
host_timeout_ctrl_rd_A	399229137	1259	0	0
intr_enable_rd_A	399229137	6489	0	0
ovrd_rd_A	399229137	1575	0	0
target_fifo_config_rd_A	399229137	1611	0	0
target_id_rd_A	399229137	2213	0	0
target_timeout_ctrl_rd_A	399229137	1657	0	0
timeout_ctrl_rd_A	399229137	1865	0	0
timing0_rd_A	399229137	1669	0	0
timing1_rd_A	399229137	1491	0	0
timing2_rd_A	399229137	1557	0	0
timing3_rd_A	399229137	1635	0	0
timing4_rd_A	399229137	1565	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	2865	0	0
T102	5219	32	0	0
T103	2866	32	0	0
T104	4701	9	0	0
T105	2705	29	0	0
T106	45881	222	0	0
T107	12500	210	0	0
T108	13183	6	0	0
T109	6021	53	0	0
T110	12846	290	0	0
T111	13056	165	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	4083	0	0
T14	792339	0	0	0
T32	251891	0	0	0
T58	547154	0	0	0
T81	468643	101	0	0
T112	0	198	0	0
T113	0	195	0	0
T114	0	99	0	0
T115	0	159	0	0
T116	0	226	0	0
T117	0	52	0	0
T118	0	148	0	0
T119	0	272	0	0
T120	0	172	0	0
T121	89947	0	0	0
T122	14374	0	0	0
T123	93182	0	0	0
T124	113642	0	0	0
T125	62228	0	0	0
T126	103089	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1659	0	0
T102	5219	21	0	0
T103	2866	23	0	0
T104	4701	7	0	0
T105	2705	9	0	0
T106	45881	304	0	0
T107	12500	80	0	0
T108	13183	19	0	0
T109	6021	74	0	0
T110	12846	123	0	0
T127	2074	14	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1259	0	0
T102	5219	23	0	0
T103	2866	15	0	0
T104	4701	16	0	0
T105	2705	5	0	0
T106	45881	274	0	0
T107	12500	36	0	0
T108	13183	31	0	0
T109	6021	63	0	0
T110	12846	78	0	0
T127	2074	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	6489	0	0
T102	0	9	0	0
T103	0	139	0	0
T104	0	12	0	0
T105	0	72	0	0
T106	0	295	0	0
T107	0	379	0	0
T108	0	36	0	0
T118	534536	22	0	0
T128	0	13	0	0
T129	0	28	0	0
T130	7312	0	0	0
T131	46661	0	0	0
T132	11030	0	0	0
T133	15027	0	0	0
T134	21394	0	0	0
T135	18461	0	0	0
T136	321551	0	0	0
T137	257851	0	0	0
T138	502708	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1575	0	0
T30	117124	0	0	0
T31	114201	0	0	0
T34	12136	0	0	0
T42	17911	0	0	0
T43	11618	0	0	0
T64	59489	0	0	0
T70	14529	0	0	0
T98	1220	0	0	0
T100	2137	90	0	0
T139	0	30	0	0
T140	0	44	0	0
T141	0	44	0	0
T142	0	55	0	0
T143	0	58	0	0
T144	0	50	0	0
T145	0	75	0	0
T146	0	50	0	0
T147	0	41	0	0
T148	67017	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1611	0	0
T102	5219	13	0	0
T103	2866	14	0	0
T105	2705	8	0	0
T106	45881	302	0	0
T107	12500	63	0	0
T108	13183	34	0	0
T109	6021	78	0	0
T110	12846	110	0	0
T111	13056	67	0	0
T127	2074	2	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	2213	0	0
T102	5219	6	0	0
T103	2866	31	0	0
T104	4701	9	0	0
T105	2705	15	0	0
T106	45881	346	0	0
T107	12500	135	0	0
T108	13183	17	0	0
T109	6021	59	0	0
T110	12846	166	0	0
T127	2074	15	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1657	0	0
T102	5219	20	0	0
T103	2866	17	0	0
T105	2705	12	0	0
T106	45881	282	0	0
T107	12500	57	0	0
T108	13183	8	0	0
T109	6021	88	0	0
T110	12846	98	0	0
T111	13056	65	0	0
T127	2074	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1865	0	0
T102	5219	15	0	0
T103	2866	31	0	0
T105	2705	16	0	0
T106	45881	295	0	0
T107	12500	65	0	0
T108	13183	16	0	0
T109	6021	71	0	0
T110	12846	138	0	0
T111	13056	132	0	0
T127	2074	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1669	0	0
T102	5219	16	0	0
T103	2866	16	0	0
T104	4701	13	0	0
T105	2705	12	0	0
T106	45881	293	0	0
T107	12500	83	0	0
T108	13183	6	0	0
T109	6021	78	0	0
T110	12846	108	0	0
T127	2074	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1491	0	0
T103	2866	17	0	0
T104	4701	6	0	0
T105	2705	8	0	0
T106	45881	275	0	0
T107	12500	76	0	0
T108	13183	22	0	0
T109	6021	56	0	0
T110	12846	90	0	0
T111	13056	62	0	0
T127	2074	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1557	0	0
T102	5219	9	0	0
T103	2866	21	0	0
T104	4701	12	0	0
T105	2705	10	0	0
T106	45881	264	0	0
T107	12500	63	0	0
T108	13183	17	0	0
T109	6021	39	0	0
T110	12846	107	0	0
T127	2074	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1635	0	0
T102	5219	28	0	0
T103	2866	14	0	0
T104	4701	2	0	0
T105	2705	4	0	0
T106	45881	306	0	0
T107	12500	101	0	0
T108	13183	48	0	0
T109	6021	65	0	0
T110	12846	92	0	0
T127	2074	10	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399229137	1565	0	0
T102	5219	17	0	0
T103	2866	18	0	0
T104	4701	9	0	0
T105	2705	8	0	0
T106	45881	248	0	0
T107	12500	71	0	0
T108	13183	33	0	0
T109	6021	61	0	0
T110	12846	130	0	0
T127	2074	3	0	0