Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_sda_override_cg

Group : i2c_env_pkg::i2c_scl_sda_override_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.scl_sda_override_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.scl_sda_override_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.scl_sda_override_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_sclval	2	0	2	100.00	100	1	1	2
cp_sdaval	2	0	2	100.00	100	1	1	2
cp_txorvden	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_txorvden_x_sclval	4	0	4	100.00	100	1	1	0
cp_txorvden_x_sdaval	4	0	4	100.00	100	1	1	0

Summary for Variable cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sclval

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

360

1

T1

12

T77

8

T101

4

auto[1]

364

1

T1

6

T77

3

T101

6

---

Summary for Variable cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sdaval

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

355

1

T1

8

T77

5

T101

4

auto[1]

369

1

T1

10

T77

6

T101

6

---

Summary for Variable cp_txorvden

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txorvden

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357

1

T1

9

T77

3

T101

7

auto[1]

367

1

T1

9

T77

8

T101

3

---

Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins

cp_txorvden

cp_sclval

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

166

1

T1

5

T77

1

T101

3

auto[0]

auto[1]

191

1

T1

4

T77

2

T101

4

auto[1]

auto[0]

194

1

T1

7

T77

7

T101

1

auto[1]

auto[1]

173

1

T1

2

T77

1

T101

2

---

Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins

cp_txorvden

cp_sdaval

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

178

1

T1

5

T77

2

T101

4

auto[0]

auto[1]

179

1

T1

4

T77

1

T101

3

auto[1]

auto[0]

177

1

T1

3

T77

3

T146

4

auto[1]

auto[1]

190

1

T1

6

T77

5

T101

3