Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30856163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7799675

1

T1

21

T2

4563

T3

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37810135	1			T1	19		T2	15246		T3	127
values[0x0]	422215	1			T1	10		T2	408		T3	53
values[0x1]	423488	1			T1	11		T2	385		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21505199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17150639

1

T1

24

T2

7757

T3

105

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	155385	1			T2	73		T6	20		T7	1
valid_sources[0x01]	151851	1			T2	65		T4	21		T6	15
valid_sources[0x02]	149693	1			T2	68		T4	4		T6	24
valid_sources[0x03]	140439	1			T2	72		T4	9		T6	17
valid_sources[0x04]	157305	1			T2	71		T4	10		T6	15
valid_sources[0x05]	150631	1			T2	50		T4	10		T6	23
valid_sources[0x06]	158365	1			T2	55		T4	10		T6	10
valid_sources[0x07]	161684	1			T2	65		T4	9		T6	20
valid_sources[0x08]	154254	1			T2	56		T4	3		T6	12
valid_sources[0x09]	166662	1			T2	69		T4	9		T6	15
valid_sources[0x0a]	143428	1			T2	53		T6	22		T8	3
valid_sources[0x0b]	158131	1			T2	68		T4	16		T6	19
valid_sources[0x0c]	154594	1			T2	55		T4	8		T6	19
valid_sources[0x0d]	150314	1			T2	65		T6	15		T8	4
valid_sources[0x0e]	152192	1			T2	61		T4	1		T6	23
valid_sources[0x0f]	146169	1			T2	70		T4	12		T6	19
valid_sources[0x10]	138300	1			T2	63		T4	2		T6	26
valid_sources[0x11]	160545	1			T2	58		T4	9		T6	23
valid_sources[0x12]	135593	1			T2	72		T4	3		T6	27
valid_sources[0x13]	152778	1			T2	52		T4	21		T6	26
valid_sources[0x14]	138159	1			T2	55		T4	17		T6	18
valid_sources[0x15]	148930	1			T2	62		T4	7		T6	21
valid_sources[0x16]	157044	1			T2	48		T3	11		T4	14
valid_sources[0x17]	156001	1			T2	55		T4	21		T6	12
valid_sources[0x18]	157388	1			T2	61		T4	12		T6	19
valid_sources[0x19]	136336	1			T2	73		T4	16		T6	13
valid_sources[0x1a]	149911	1			T2	50		T4	6		T6	18
valid_sources[0x1b]	153499	1			T2	58		T3	5		T4	3
valid_sources[0x1c]	143642	1			T2	49		T3	1		T4	7
valid_sources[0x1d]	142207	1			T2	53		T4	8		T6	16
valid_sources[0x1e]	155288	1			T2	52		T4	4		T6	17
valid_sources[0x1f]	150366	1			T2	66		T4	10		T6	20
valid_sources[0x20]	142139	1			T2	73		T4	8		T6	21
valid_sources[0x21]	146929	1			T2	61		T3	10		T4	17
valid_sources[0x22]	154546	1			T2	60		T4	10		T6	10
valid_sources[0x23]	143949	1			T2	60		T4	22		T6	27
valid_sources[0x24]	145377	1			T2	68		T4	8		T6	16
valid_sources[0x25]	153285	1			T2	66		T4	4		T6	20
valid_sources[0x26]	151323	1			T2	66		T4	3		T6	28
valid_sources[0x27]	150795	1			T2	63		T3	32		T4	12
valid_sources[0x28]	149785	1			T2	53		T4	9		T6	15
valid_sources[0x29]	138791	1			T2	67		T3	1		T4	10
valid_sources[0x2a]	147232	1			T2	63		T4	4		T6	16
valid_sources[0x2b]	149590	1			T2	57		T4	8		T6	20
valid_sources[0x2c]	155391	1			T2	49		T4	10		T6	27
valid_sources[0x2d]	150464	1			T2	72		T4	6		T6	11
valid_sources[0x2e]	165625	1			T2	72		T4	24		T6	14
valid_sources[0x2f]	143429	1			T2	58		T3	2		T4	13
valid_sources[0x30]	155320	1			T2	61		T4	6		T5	2057
valid_sources[0x31]	205822	1			T2	57		T4	17		T6	14
valid_sources[0x32]	144409	1			T2	57		T4	9		T6	20
valid_sources[0x33]	167606	1			T2	84		T4	4		T6	31
valid_sources[0x34]	168007	1			T2	58		T4	15		T6	10
valid_sources[0x35]	152925	1			T2	85		T4	1		T6	14
valid_sources[0x36]	147812	1			T2	64		T4	6		T6	17
valid_sources[0x37]	146494	1			T2	63		T4	8		T6	28
valid_sources[0x38]	145213	1			T2	62		T4	13		T6	28
valid_sources[0x39]	151023	1			T2	70		T4	17		T6	26
valid_sources[0x3a]	149375	1			T2	56		T4	10		T6	22
valid_sources[0x3b]	139120	1			T2	61		T4	4		T6	16
valid_sources[0x3c]	147876	1			T2	65		T4	4		T6	16
valid_sources[0x3d]	154660	1			T2	53		T4	13		T6	15
valid_sources[0x3e]	149431	1			T2	77		T4	16		T6	23
valid_sources[0x3f]	159430	1			T2	60		T4	8		T6	16
valid_sources[0x40]	152206	1			T2	67		T4	7		T6	14
valid_sources[0x41]	138757	1			T2	67		T4	4		T6	25
valid_sources[0x42]	173774	1			T2	63		T4	4		T6	21
valid_sources[0x43]	143913	1			T2	56		T4	6		T6	15
valid_sources[0x44]	148152	1			T2	79		T4	12		T6	21
valid_sources[0x45]	151724	1			T2	55		T6	20		T7	10
valid_sources[0x46]	152555	1			T2	65		T4	3		T6	10
valid_sources[0x47]	147210	1			T2	55		T3	6		T4	6
valid_sources[0x48]	138505	1			T2	79		T4	11		T6	16
valid_sources[0x49]	141720	1			T2	68		T4	3		T6	23
valid_sources[0x4a]	152025	1			T2	62		T4	4		T6	16
valid_sources[0x4b]	161345	1			T2	55		T4	4		T6	16
valid_sources[0x4c]	160995	1			T2	76		T4	8		T6	22
valid_sources[0x4d]	140006	1			T2	59		T4	3		T6	15
valid_sources[0x4e]	139817	1			T2	64		T4	11		T6	27
valid_sources[0x4f]	148561	1			T2	73		T4	8		T6	14
valid_sources[0x50]	143917	1			T2	68		T4	7		T6	12
valid_sources[0x51]	154996	1			T2	54		T4	2		T6	27
valid_sources[0x52]	163029	1			T2	59		T4	1		T6	16
valid_sources[0x53]	164384	1			T2	64		T4	5		T6	24
valid_sources[0x54]	152299	1			T2	52		T4	16		T6	16
valid_sources[0x55]	149703	1			T2	81		T4	16		T6	21
valid_sources[0x56]	145203	1			T2	66		T4	3		T6	15
valid_sources[0x57]	160806	1			T2	53		T4	4		T6	16
valid_sources[0x58]	147268	1			T2	52		T3	3		T4	16
valid_sources[0x59]	158868	1			T2	79		T4	6		T6	20
valid_sources[0x5a]	142694	1			T2	61		T4	12		T6	27
valid_sources[0x5b]	150562	1			T2	64		T4	15		T6	33
valid_sources[0x5c]	146190	1			T2	57		T4	9		T6	15
valid_sources[0x5d]	169709	1			T2	61		T4	6		T6	14
valid_sources[0x5e]	139955	1			T2	75		T3	8		T4	3
valid_sources[0x5f]	158249	1			T2	66		T3	2		T6	13
valid_sources[0x60]	144703	1			T2	57		T3	3		T4	3
valid_sources[0x61]	150697	1			T2	66		T4	1		T6	25
valid_sources[0x62]	147055	1			T2	65		T4	4		T6	32
valid_sources[0x63]	145977	1			T2	41		T4	6		T6	28
valid_sources[0x64]	154375	1			T2	69		T4	4		T6	19
valid_sources[0x65]	150697	1			T2	57		T4	4		T6	22
valid_sources[0x66]	150895	1			T2	66		T4	8		T6	24
valid_sources[0x67]	158952	1			T2	75		T4	14		T6	25
valid_sources[0x68]	147585	1			T2	57		T4	2		T6	17
valid_sources[0x69]	155226	1			T2	65		T4	16		T6	25
valid_sources[0x6a]	148079	1			T2	72		T4	4		T6	25
valid_sources[0x6b]	151722	1			T2	47		T4	7		T6	11
valid_sources[0x6c]	143750	1			T2	59		T4	3		T6	23
valid_sources[0x6d]	155856	1			T2	81		T4	4		T6	21
valid_sources[0x6e]	148753	1			T2	57		T4	15		T6	21
valid_sources[0x6f]	148179	1			T2	53		T4	9		T6	20
valid_sources[0x70]	152237	1			T2	62		T4	3		T6	20
valid_sources[0x71]	149708	1			T2	46		T4	1		T6	26
valid_sources[0x72]	157997	1			T2	63		T4	5		T6	18
valid_sources[0x73]	148027	1			T2	77		T4	6		T6	15
valid_sources[0x74]	153617	1			T2	79		T4	8		T6	14
valid_sources[0x75]	159489	1			T2	43		T4	12		T6	15
valid_sources[0x76]	146644	1			T2	57		T4	12		T6	22
valid_sources[0x77]	159267	1			T2	74		T4	2		T6	18
valid_sources[0x78]	158142	1			T2	63		T4	10		T6	14
valid_sources[0x79]	144619	1			T2	70		T6	20		T7	1
valid_sources[0x7a]	149188	1			T2	62		T4	2		T6	17
valid_sources[0x7b]	145602	1			T2	76		T4	5		T6	19
valid_sources[0x7c]	145534	1			T2	73		T4	8		T6	14
valid_sources[0x7d]	150721	1			T2	66		T4	14		T6	20
valid_sources[0x7e]	176444	1			T2	74		T4	9		T6	17
valid_sources[0x7f]	151223	1			T2	61		T4	2		T6	25
valid_sources[0x80]	148971	1			T2	66		T3	5		T4	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7430373

1

T1

11

T2

4076

T3

2

values[0x0]

all_enables

biggest_size

220555

1

T1

6

T2

259

T3

28

values[0x1]

all_enables

biggest_size

148747

1

T1

4

T2

228

T3

17