Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28851802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7804847

1

T1

9

T2

5132

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35874211	1			T1	12		T2	18013		T3	81
values[0x0]	390967	1			T1	2		T2	342		T3	40
values[0x1]	391471	1			T1	8		T2	331		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20150736	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16505913

1

T1

13

T2

8960

T3

65

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146862	1			T2	74		T4	16		T5	12
valid_sources[0x01]	129148	1			T2	76		T4	12		T5	16
valid_sources[0x02]	132133	1			T2	86		T4	10		T5	24
valid_sources[0x03]	134066	1			T1	3		T2	79		T3	5
valid_sources[0x04]	143859	1			T2	92		T4	10		T5	20
valid_sources[0x05]	125966	1			T2	68		T4	12		T5	14
valid_sources[0x06]	147380	1			T2	73		T3	11		T4	7
valid_sources[0x07]	144632	1			T2	86		T4	13		T5	14
valid_sources[0x08]	144301	1			T2	90		T4	10		T5	17
valid_sources[0x09]	147609	1			T2	68		T4	12		T5	20
valid_sources[0x0a]	132359	1			T2	81		T4	10		T5	13
valid_sources[0x0b]	133315	1			T2	65		T4	7		T5	20
valid_sources[0x0c]	189183	1			T2	83		T4	5		T5	16
valid_sources[0x0d]	137657	1			T1	3		T2	75		T4	12
valid_sources[0x0e]	138567	1			T2	65		T4	14		T5	10
valid_sources[0x0f]	144079	1			T2	65		T4	8		T5	19
valid_sources[0x10]	150921	1			T2	76		T4	8		T5	27
valid_sources[0x11]	132814	1			T2	77		T4	14		T5	17
valid_sources[0x12]	145302	1			T2	72		T4	6		T5	15
valid_sources[0x13]	121611	1			T2	87		T4	19		T5	15
valid_sources[0x14]	156855	1			T2	64		T4	8		T5	15
valid_sources[0x15]	161294	1			T2	82		T4	7		T5	29
valid_sources[0x16]	137686	1			T2	74		T4	14		T5	21
valid_sources[0x17]	152567	1			T2	71		T4	7		T5	26
valid_sources[0x18]	128502	1			T2	85		T4	9		T5	25
valid_sources[0x19]	141748	1			T2	68		T3	3		T4	15
valid_sources[0x1a]	147305	1			T2	83		T4	14		T5	13
valid_sources[0x1b]	137366	1			T2	78		T4	14		T5	15
valid_sources[0x1c]	149526	1			T2	84		T4	13		T5	13
valid_sources[0x1d]	147426	1			T2	87		T4	19		T5	14
valid_sources[0x1e]	156168	1			T2	79		T4	7		T5	14
valid_sources[0x1f]	149169	1			T2	73		T4	10		T5	14
valid_sources[0x20]	148832	1			T2	62		T4	15		T5	11
valid_sources[0x21]	156688	1			T2	68		T4	5		T5	17
valid_sources[0x22]	157861	1			T2	54		T4	11		T5	17
valid_sources[0x23]	156516	1			T2	82		T4	22		T5	7
valid_sources[0x24]	137944	1			T2	86		T4	10		T5	8
valid_sources[0x25]	146977	1			T2	101		T4	14		T5	15
valid_sources[0x26]	139026	1			T2	54		T4	9		T5	14
valid_sources[0x27]	150779	1			T2	88		T3	6		T4	11
valid_sources[0x28]	139298	1			T2	59		T4	8		T5	13
valid_sources[0x29]	141601	1			T2	52		T4	19		T5	17
valid_sources[0x2a]	129607	1			T2	77		T4	11		T5	21
valid_sources[0x2b]	162236	1			T2	87		T4	17		T5	18
valid_sources[0x2c]	137454	1			T2	75		T4	13		T5	10
valid_sources[0x2d]	143019	1			T2	76		T4	6		T5	18
valid_sources[0x2e]	139960	1			T2	74		T3	4		T4	16
valid_sources[0x2f]	154431	1			T2	75		T4	8		T5	12
valid_sources[0x30]	125598	1			T2	86		T4	11		T5	15
valid_sources[0x31]	155904	1			T2	92		T4	4		T5	21
valid_sources[0x32]	133625	1			T2	63		T4	22		T5	15
valid_sources[0x33]	145409	1			T2	76		T3	1		T4	7
valid_sources[0x34]	128608	1			T2	66		T4	11		T5	10
valid_sources[0x35]	157484	1			T2	66		T4	12		T5	12
valid_sources[0x36]	143658	1			T2	69		T4	9		T5	21
valid_sources[0x37]	143595	1			T2	76		T4	8		T5	24
valid_sources[0x38]	132947	1			T2	72		T4	13		T5	15
valid_sources[0x39]	144388	1			T2	82		T4	12		T5	25
valid_sources[0x3a]	131332	1			T2	80		T4	14		T5	17
valid_sources[0x3b]	138453	1			T2	70		T4	14		T5	16
valid_sources[0x3c]	139623	1			T2	63		T4	11		T5	18
valid_sources[0x3d]	143974	1			T2	74		T4	8		T5	17
valid_sources[0x3e]	150859	1			T2	67		T4	8		T5	16
valid_sources[0x3f]	139114	1			T1	1		T2	74		T4	5
valid_sources[0x40]	158810	1			T1	4		T2	69		T4	9
valid_sources[0x41]	141148	1			T2	78		T4	8		T5	20
valid_sources[0x42]	138747	1			T2	52		T4	5		T5	20
valid_sources[0x43]	154054	1			T2	64		T4	6		T5	20
valid_sources[0x44]	139674	1			T2	81		T4	4		T5	17
valid_sources[0x45]	137944	1			T2	64		T4	7		T5	17
valid_sources[0x46]	127965	1			T2	65		T4	7		T5	18
valid_sources[0x47]	131892	1			T2	93		T4	14		T5	20
valid_sources[0x48]	136384	1			T2	58		T4	9		T5	10
valid_sources[0x49]	146923	1			T2	67		T4	12		T5	19
valid_sources[0x4a]	134558	1			T2	77		T3	2		T4	15
valid_sources[0x4b]	144124	1			T2	85		T4	18		T5	19
valid_sources[0x4c]	147341	1			T2	70		T4	7		T5	30
valid_sources[0x4d]	129079	1			T2	76		T4	3		T5	22
valid_sources[0x4e]	149641	1			T1	3		T2	66		T3	23
valid_sources[0x4f]	152456	1			T2	82		T4	14		T5	13
valid_sources[0x50]	124848	1			T2	69		T4	7		T5	12
valid_sources[0x51]	133992	1			T2	63		T3	2		T4	5
valid_sources[0x52]	132981	1			T2	79		T3	17		T4	9
valid_sources[0x53]	130728	1			T2	82		T4	7		T5	19
valid_sources[0x54]	139548	1			T2	65		T4	10		T5	17
valid_sources[0x55]	130372	1			T2	67		T4	8		T5	19
valid_sources[0x56]	152122	1			T2	81		T4	20		T5	16
valid_sources[0x57]	137557	1			T2	82		T4	10		T5	19
valid_sources[0x58]	132222	1			T2	65		T4	12		T5	17
valid_sources[0x59]	147726	1			T2	78		T3	18		T4	9
valid_sources[0x5a]	146625	1			T2	60		T4	8		T5	11
valid_sources[0x5b]	135211	1			T2	59		T3	1		T4	8
valid_sources[0x5c]	144716	1			T1	1		T2	77		T4	6
valid_sources[0x5d]	134115	1			T2	68		T4	15		T5	15
valid_sources[0x5e]	144266	1			T2	67		T4	13		T5	19
valid_sources[0x5f]	137605	1			T2	80		T4	14		T5	21
valid_sources[0x60]	144051	1			T2	65		T4	10		T5	26
valid_sources[0x61]	129340	1			T2	65		T3	8		T4	9
valid_sources[0x62]	148211	1			T2	84		T4	5		T5	23
valid_sources[0x63]	123816	1			T2	65		T4	3		T5	16
valid_sources[0x64]	160079	1			T2	56		T4	14		T5	10
valid_sources[0x65]	147983	1			T2	78		T4	8		T5	7
valid_sources[0x66]	143742	1			T2	72		T4	11		T5	18
valid_sources[0x67]	151514	1			T2	55		T4	8		T5	12
valid_sources[0x68]	133206	1			T2	85		T4	18		T5	10
valid_sources[0x69]	136749	1			T2	78		T4	12		T5	13
valid_sources[0x6a]	133598	1			T2	63		T3	5		T4	12
valid_sources[0x6b]	135401	1			T2	75		T4	14		T5	17
valid_sources[0x6c]	137147	1			T2	71		T4	9		T5	20
valid_sources[0x6d]	143176	1			T2	52		T4	11		T5	24
valid_sources[0x6e]	130005	1			T2	86		T4	13		T5	9
valid_sources[0x6f]	136122	1			T2	72		T4	18		T5	14
valid_sources[0x70]	141884	1			T2	70		T4	10		T5	7
valid_sources[0x71]	137673	1			T2	70		T4	14		T5	21
valid_sources[0x72]	133879	1			T2	59		T4	8		T5	13
valid_sources[0x73]	136160	1			T2	72		T4	17		T5	19
valid_sources[0x74]	143230	1			T2	70		T4	17		T5	18
valid_sources[0x75]	136016	1			T2	65		T4	14		T5	17
valid_sources[0x76]	156544	1			T2	69		T4	9		T5	16
valid_sources[0x77]	141990	1			T2	70		T4	11		T5	14
valid_sources[0x78]	140206	1			T2	77		T3	3		T4	7
valid_sources[0x79]	133923	1			T2	76		T4	17		T5	24
valid_sources[0x7a]	146264	1			T2	70		T4	10		T5	16
valid_sources[0x7b]	172010	1			T2	75		T3	1		T4	6
valid_sources[0x7c]	149541	1			T2	81		T4	5		T5	16
valid_sources[0x7d]	146716	1			T2	72		T4	10		T5	23
valid_sources[0x7e]	123054	1			T2	80		T4	6		T5	22
valid_sources[0x7f]	141967	1			T2	82		T4	16		T5	9
valid_sources[0x80]	139132	1			T1	1		T2	82		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7457561

1

T1

5

T2

4718

T4

968

values[0x0]

all_enables

biggest_size

206125

1

T1

1

T2

231

T3

26

values[0x1]

all_enables

biggest_size

141161

1

T1

3

T2

183

T3

10