Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838973	1			T1	1		T2	2		T3	12
all_values[1]	838973	1			T1	1		T2	2		T3	12
all_values[2]	838973	1			T1	1		T2	2		T3	12
all_values[3]	838973	1			T1	1		T2	2		T3	12
all_values[4]	838973	1			T1	1		T2	2		T3	12
all_values[5]	838973	1			T1	1		T2	2		T3	12
all_values[6]	838973	1			T1	1		T2	2		T3	12
all_values[7]	838973	1			T1	1		T2	2		T3	12
all_values[8]	838973	1			T1	1		T2	2		T3	12
all_values[9]	838973	1			T1	1		T2	2		T3	12
all_values[10]	838973	1			T1	1		T2	2		T3	12
all_values[11]	838973	1			T1	1		T2	2		T3	12
all_values[12]	838973	1			T1	1		T2	2		T3	12
all_values[13]	838973	1			T1	1		T2	2		T3	12
all_values[14]	838973	1			T1	1		T2	2		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10392444

1

T1

15

T2

30

T3

160

auto[1]

2192151

1

T3

20

T5

4

T6

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11597067

1

T1

15

T2

30

T3

180

auto[1]

987528

1

T198

1338

T199

21718

T20

116668

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	128872	1			T1	1		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	7103	1			T198	13		T199	1073		T20	935
all_values[0]	auto[1]	auto[0]	639593	1			T3	10		T5	2		T6	4
all_values[0]	auto[1]	auto[1]	63405	1			T198	77		T199	529		T20	6843
all_values[1]	auto[0]	auto[0]	787296	1			T1	1		T2	2		T3	12
all_values[1]	auto[0]	auto[1]	51317	1			T198	86		T199	1598		T20	7768
all_values[1]	auto[1]	auto[0]	209	1			T31	1		T152	30		T271	1
all_values[1]	auto[1]	auto[1]	151	1			T198	5		T199	6		T20	9
all_values[2]	auto[0]	auto[0]	768284	1			T1	1		T2	2		T3	12
all_values[2]	auto[0]	auto[1]	70366	1			T198	84		T199	1597		T20	7777
all_values[2]	auto[1]	auto[0]	191	1			T49	1		T171	2		T65	1
all_values[2]	auto[1]	auto[1]	132	1			T198	4		T199	7		T20	1
all_values[3]	auto[0]	auto[0]	768494	1			T1	1		T2	2		T3	12
all_values[3]	auto[0]	auto[1]	70317	1			T198	85		T199	1597		T20	7776
all_values[3]	auto[1]	auto[1]	162	1			T198	4		T199	9		T20	2
all_values[4]	auto[0]	auto[0]	787489	1			T1	1		T2	2		T3	12
all_values[4]	auto[0]	auto[1]	51320	1			T198	85		T199	1595		T20	7776
all_values[4]	auto[1]	auto[0]	25	1			T11	1		T267	1		T272	1
all_values[4]	auto[1]	auto[1]	139	1			T198	5		T199	9		T20	2
all_values[5]	auto[0]	auto[0]	768479	1			T1	1		T2	2		T3	12
all_values[5]	auto[0]	auto[1]	70325	1			T198	88		T199	1600		T20	7776
all_values[5]	auto[1]	auto[1]	169	1			T198	3		T199	6		T20	1
all_values[6]	auto[0]	auto[0]	768479	1			T1	1		T2	2		T3	12
all_values[6]	auto[0]	auto[1]	70331	1			T198	85		T199	1596		T20	7775
all_values[6]	auto[1]	auto[1]	163	1			T198	5		T199	9		T20	3
all_values[7]	auto[0]	auto[0]	739812	1			T1	1		T2	2		T3	12
all_values[7]	auto[0]	auto[1]	68614	1			T198	78		T199	1322		T20	7302
all_values[7]	auto[1]	auto[0]	28654	1			T8	3		T9	1		T24	14
all_values[7]	auto[1]	auto[1]	1893	1			T198	12		T199	284		T20	476
all_values[8]	auto[0]	auto[0]	783994	1			T1	1		T2	2		T3	12
all_values[8]	auto[0]	auto[1]	54829	1			T198	84		T199	845		T20	7777
all_values[8]	auto[1]	auto[1]	150	1			T198	6		T199	3		T20	1
all_values[9]	auto[0]	auto[0]	203243	1			T1	1		T2	2		T3	12
all_values[9]	auto[0]	auto[1]	15533	1			T198	87		T199	1561		T20	1143
all_values[9]	auto[1]	auto[0]	579980	1			T6	1		T8	2		T9	1
all_values[9]	auto[1]	auto[1]	40217	1			T198	4		T199	45		T20	6635
all_values[10]	auto[0]	auto[0]	768471	1			T1	1		T2	2		T3	12
all_values[10]	auto[0]	auto[1]	70350	1			T198	86		T199	1598		T20	7776
all_values[10]	auto[1]	auto[1]	152	1			T198	4		T199	7		T20	2
all_values[11]	auto[0]	auto[0]	2427	1			T1	1		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	312	1			T198	14		T199	12		T20	38
all_values[11]	auto[1]	auto[0]	766048	1			T3	10		T5	2		T6	4
all_values[11]	auto[1]	auto[1]	70186	1			T198	77		T199	1594		T20	7740
all_values[12]	auto[0]	auto[0]	768399	1			T1	1		T2	2		T3	12
all_values[12]	auto[0]	auto[1]	70356	1			T198	86		T199	1600		T20	7776
all_values[12]	auto[1]	auto[0]	61	1			T49	1		T65	1		T70	1
all_values[12]	auto[1]	auto[1]	157	1			T198	5		T199	6		T20	2
all_values[13]	auto[0]	auto[0]	770064	1			T1	1		T2	2		T3	12
all_values[13]	auto[0]	auto[1]	68751	1			T198	89		T199	2		T20	7778
all_values[13]	auto[1]	auto[1]	158	1			T198	2		T199	7		T244	3
all_values[14]	auto[0]	auto[0]	768503	1			T1	1		T2	2		T3	12
all_values[14]	auto[0]	auto[1]	70314	1			T198	72		T199	1593		T20	7776
all_values[14]	auto[1]	auto[1]	156	1			T198	3		T199	8		T20	2