Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.14 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 19 0 19 100.00
Crosses 60 7 53 88.33


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 15 0 15 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 60 7 53 88.33 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 732188 1 T1 1 T2 2 T3 34
all_values[1] 732188 1 T1 1 T2 2 T3 34
all_values[2] 732188 1 T1 1 T2 2 T3 34
all_values[3] 732188 1 T1 1 T2 2 T3 34
all_values[4] 732188 1 T1 1 T2 2 T3 34
all_values[5] 732188 1 T1 1 T2 2 T3 34
all_values[6] 732188 1 T1 1 T2 2 T3 34
all_values[7] 732188 1 T1 1 T2 2 T3 34
all_values[8] 732188 1 T1 1 T2 2 T3 34
all_values[9] 732188 1 T1 1 T2 2 T3 34
all_values[10] 732188 1 T1 1 T2 2 T3 34
all_values[11] 732188 1 T1 1 T2 2 T3 34
all_values[12] 732188 1 T1 1 T2 2 T3 34
all_values[13] 732188 1 T1 1 T2 2 T3 34
all_values[14] 732188 1 T1 1 T2 2 T3 34


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 9035965 1 T1 15 T2 30 T3 443
auto[1] 1946855 1 T3 67 T4 6 T5 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10541479 1 T1 15 T2 30 T3 510
auto[1] 441341 1 T23 23580 T111 29363 T180 71


Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 7 53 88.33 7


Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   NUMBER   STATUS   
[all_values[3]] [auto[1]] [auto[0]] 0 1 1
[all_values[5] , all_values[6]] [auto[1]] [auto[0]] -- -- 2
[all_values[8]] [auto[1]] [auto[0]] 0 1 1
[all_values[10]] [auto[1]] [auto[0]] 0 1 1
[all_values[13] , all_values[14]] [auto[1]] [auto[0]] -- -- 2


Covered bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 102258 1 T1 1 T2 2 T3 4
all_values[0] auto[0] auto[1] 7859 1 T23 875 T111 87 T180 3
all_values[0] auto[1] auto[0] 600221 1 T3 30 T4 2 T5 2
all_values[0] auto[1] auto[1] 21850 1 T23 697 T111 1872 T180 3
all_values[1] auto[0] auto[0] 702149 1 T1 1 T2 2 T3 34
all_values[1] auto[0] auto[1] 29551 1 T23 1568 T111 1954 T180 3
all_values[1] auto[1] auto[0] 321 1 T26 2 T263 54 T264 5
all_values[1] auto[1] auto[1] 167 1 T23 4 T111 5 T180 1
all_values[2] auto[0] auto[0] 702300 1 T1 1 T2 2 T3 34
all_values[2] auto[0] auto[1] 29553 1 T23 1566 T111 1949 T180 4
all_values[2] auto[1] auto[0] 189 1 T162 1 T189 1 T64 1
all_values[2] auto[1] auto[1] 146 1 T23 2 T111 10 T180 1
all_values[3] auto[0] auto[0] 703623 1 T1 1 T2 2 T3 34
all_values[3] auto[0] auto[1] 28404 1 T23 1567 T111 1949 T180 2
all_values[3] auto[1] auto[1] 161 1 T23 5 T111 9 T180 3
all_values[4] auto[0] auto[0] 702463 1 T1 1 T2 2 T3 34
all_values[4] auto[0] auto[1] 29556 1 T23 1568 T111 1951 T180 5
all_values[4] auto[1] auto[0] 17 1 T11 1 T245 3 T246 1
all_values[4] auto[1] auto[1] 152 1 T23 5 T111 7 T180 1
all_values[5] auto[0] auto[0] 702505 1 T1 1 T2 2 T3 34
all_values[5] auto[0] auto[1] 29526 1 T23 1564 T111 1947 T180 2
all_values[5] auto[1] auto[1] 157 1 T23 9 T111 4 T180 3
all_values[6] auto[0] auto[0] 705186 1 T1 1 T2 2 T3 34
all_values[6] auto[0] auto[1] 26823 1 T23 1568 T111 1949 T180 4
all_values[6] auto[1] auto[1] 179 1 T23 5 T111 10 T180 2
all_values[7] auto[0] auto[0] 673444 1 T1 1 T2 2 T3 27
all_values[7] auto[0] auto[1] 28800 1 T23 1462 T111 1833 T180 4
all_values[7] auto[1] auto[0] 29037 1 T3 7 T4 1 T5 1
all_values[7] auto[1] auto[1] 907 1 T23 111 T111 124 T41 7
all_values[8] auto[0] auto[0] 702472 1 T1 1 T2 2 T3 34
all_values[8] auto[0] auto[1] 29514 1 T23 1566 T111 1951 T180 2
all_values[8] auto[1] auto[1] 202 1 T23 4 T111 7 T180 2
all_values[9] auto[0] auto[0] 162661 1 T1 1 T2 2 T3 34
all_values[9] auto[0] auto[1] 6460 1 T23 1538 T111 52 T180 4
all_values[9] auto[1] auto[0] 539822 1 T4 1 T5 1 T9 1
all_values[9] auto[1] auto[1] 23245 1 T23 35 T111 1907 T41 6
all_values[10] auto[0] auto[0] 702480 1 T1 1 T2 2 T3 34
all_values[10] auto[0] auto[1] 29558 1 T23 1567 T111 1952 T180 4
all_values[10] auto[1] auto[1] 150 1 T23 6 T111 7 T180 1
all_values[11] auto[0] auto[0] 2510 1 T1 1 T2 2 T3 4
all_values[11] auto[0] auto[1] 290 1 T23 17 T111 22 T180 3
all_values[11] auto[1] auto[0] 700374 1 T3 30 T4 2 T5 2
all_values[11] auto[1] auto[1] 29014 1 T23 1553 T111 1931 T180 3
all_values[12] auto[0] auto[0] 702424 1 T1 1 T2 2 T3 34
all_values[12] auto[0] auto[1] 29552 1 T23 1571 T111 1951 T180 4
all_values[12] auto[1] auto[0] 63 1 T64 1 T265 1 T65 1
all_values[12] auto[1] auto[1] 149 1 T23 2 T111 6 T180 1
all_values[13] auto[0] auto[0] 702479 1 T1 1 T2 2 T3 34
all_values[13] auto[0] auto[1] 29545 1 T23 1566 T111 1949 T180 2
all_values[13] auto[1] auto[1] 164 1 T23 7 T111 10 T180 4
all_values[14] auto[0] auto[0] 702481 1 T1 1 T2 2 T3 34
all_values[14] auto[0] auto[1] 29539 1 T23 1567 T111 1947 T115 8
all_values[14] auto[1] auto[1] 168 1 T23 5 T111 11 T115 1