Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.39 97.29 89.69 97.22 72.62 94.37 98.47 90.11


Total tests in report: 1839
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.45 63.45 83.35 83.35 61.20 61.20 88.52 88.52 17.26 17.26 74.63 74.63 85.59 85.59 33.58 33.58 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.2025503354
74.72 11.27 90.52 7.17 69.70 8.51 90.14 1.62 57.74 40.48 84.18 9.55 88.43 2.84 42.32 8.74 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.1506404869
78.20 3.49 91.75 1.23 72.53 2.82 90.84 0.70 58.33 0.60 84.82 0.64 88.43 0.00 60.74 18.42 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.12951820
80.64 2.43 92.98 1.23 76.48 3.95 92.34 1.51 61.90 3.57 86.89 2.07 90.61 2.18 63.26 2.53 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.4092283209
82.88 2.24 94.31 1.32 79.68 3.20 92.81 0.46 66.67 4.76 88.60 1.71 91.05 0.44 67.05 3.79 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1723546635
84.24 1.36 94.40 0.09 80.47 0.79 94.43 1.62 66.67 0.00 88.67 0.07 94.76 3.71 70.32 3.26 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2569427187
85.46 1.21 94.92 0.52 82.12 1.66 94.66 0.23 67.26 0.60 89.74 1.07 94.98 0.22 74.53 4.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.3441460406
86.27 0.81 95.14 0.22 83.52 1.39 94.90 0.23 67.26 0.00 90.09 0.36 95.20 0.22 77.79 3.26 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2186082410
86.93 0.66 95.54 0.40 85.17 1.66 95.36 0.46 67.86 0.60 91.38 1.28 95.41 0.22 77.79 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.2316046476
87.44 0.51 95.81 0.28 85.74 0.56 95.59 0.23 67.86 0.00 92.16 0.78 95.63 0.22 79.26 1.47 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_override.1810254942
87.84 0.41 96.12 0.31 86.56 0.83 95.59 0.00 67.86 0.00 92.59 0.43 96.29 0.66 79.89 0.63 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.2255401379
88.21 0.37 96.55 0.43 86.56 0.00 95.59 0.00 69.05 1.19 93.01 0.43 96.29 0.00 80.42 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.3567119003
88.53 0.32 96.55 0.00 86.64 0.08 96.98 1.39 69.05 0.00 93.01 0.00 96.51 0.22 80.95 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.955186105
88.82 0.30 96.61 0.06 86.75 0.11 96.98 0.00 69.64 0.60 93.16 0.14 96.51 0.00 82.11 1.16 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.601186429
89.08 0.26 96.61 0.00 87.73 0.98 96.98 0.00 69.64 0.00 93.23 0.07 96.51 0.00 82.84 0.74 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1977106373
89.31 0.23 96.61 0.00 87.73 0.00 96.98 0.00 69.64 0.00 93.23 0.00 98.03 1.53 82.95 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.17389158
89.53 0.22 96.77 0.15 87.92 0.19 96.98 0.00 70.24 0.60 93.51 0.29 98.03 0.00 83.26 0.32 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3100461525
89.74 0.21 96.86 0.09 88.26 0.34 96.98 0.00 70.83 0.60 93.66 0.14 98.03 0.00 83.58 0.32 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_stress_all.997631814
89.93 0.18 96.89 0.03 88.26 0.00 96.98 0.00 71.43 0.60 93.80 0.14 98.03 0.00 84.11 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.405845637
90.10 0.17 97.01 0.12 88.37 0.11 96.98 0.00 72.02 0.60 93.94 0.14 98.03 0.00 84.32 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.3894521439
90.23 0.13 97.01 0.00 88.56 0.19 96.98 0.00 72.02 0.00 94.01 0.07 98.25 0.22 84.74 0.42 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.4242820959
90.35 0.12 97.14 0.12 88.56 0.00 96.98 0.00 72.62 0.60 94.16 0.14 98.25 0.00 84.74 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.3498397955
90.47 0.12 97.14 0.00 88.63 0.08 96.98 0.00 72.62 0.00 94.16 0.00 98.25 0.00 85.47 0.74 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.859645720
90.57 0.10 97.14 0.00 88.71 0.08 96.98 0.00 72.62 0.00 94.16 0.00 98.25 0.00 86.11 0.63 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3952303915
90.65 0.08 97.17 0.03 88.75 0.04 96.98 0.00 72.62 0.00 94.23 0.07 98.25 0.00 86.53 0.42 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.512881533
90.71 0.07 97.29 0.12 88.86 0.11 97.22 0.23 72.62 0.00 94.23 0.00 98.25 0.00 86.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3366734943
90.77 0.06 97.29 0.00 88.86 0.00 97.22 0.00 72.62 0.00 94.23 0.00 98.25 0.00 86.95 0.42 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.4126852497
90.83 0.05 97.29 0.00 88.93 0.08 97.22 0.00 72.62 0.00 94.30 0.07 98.47 0.22 86.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.1547955173
90.87 0.05 97.29 0.00 88.93 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 87.26 0.32 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.3728199232
90.92 0.05 97.29 0.00 88.93 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 87.58 0.32 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2790303216
90.96 0.05 97.29 0.00 88.93 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 87.89 0.32 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.4088094416
91.00 0.04 97.29 0.00 89.09 0.15 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 88.00 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_mode_toggle.3891086339
91.03 0.03 97.29 0.00 89.09 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 88.21 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.1204622509
91.06 0.03 97.29 0.00 89.09 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 88.42 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.875602097
91.09 0.03 97.29 0.00 89.09 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 88.63 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.4220698319
91.12 0.03 97.29 0.00 89.09 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 88.84 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.780374899
91.15 0.03 97.29 0.00 89.09 0.00 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 89.05 0.21 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.3413998136
91.17 0.03 97.29 0.00 89.16 0.08 97.22 0.00 72.62 0.00 94.30 0.00 98.47 0.00 89.16 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3787858964
91.19 0.02 97.29 0.00 89.24 0.08 97.22 0.00 72.62 0.00 94.37 0.07 98.47 0.00 89.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2788030808
91.21 0.02 97.29 0.00 89.27 0.04 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.26 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2482855579
91.23 0.02 97.29 0.00 89.39 0.11 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.422928824
91.25 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.37 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.1199093601
91.26 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.47 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1934524997
91.28 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.58 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.38226376
91.29 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.68 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.715546791
91.31 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.79 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.3071687208
91.32 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 89.89 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1733551462
91.34 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.00 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.988095955
91.35 0.02 97.29 0.00 89.39 0.00 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.3730575023
91.36 0.01 97.29 0.00 89.46 0.08 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3175916859
91.37 0.01 97.29 0.00 89.54 0.08 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1546875551
91.38 0.01 97.29 0.00 89.57 0.04 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2945791539
91.38 0.01 97.29 0.00 89.61 0.04 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.1344304595
91.39 0.01 97.29 0.00 89.65 0.04 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.2001325135
91.39 0.01 97.29 0.00 89.69 0.04 97.22 0.00 72.62 0.00 94.37 0.00 98.47 0.00 90.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.2994868001

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2413817456
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2060155456
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2971716994
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1965741192
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3414218122
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2422481220
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1735528927
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.256885338
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.573700737
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.882843018
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.519266616
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.1969155057
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.730271134
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1544717526
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1456074352
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1541535698
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2123606281
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.856824254
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.115308513
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2683385234
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3917805423
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1280427143
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2620260146
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.4107321013
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1413435043
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.1971593037
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.3707474795
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3443674873
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1121249417
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.2034531862
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3131709954
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.2898308951
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.128851297
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1342506853
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1167795797
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.595802610
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2619893260
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1555052629
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/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.1903924407
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/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.2058242384
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/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.4086147177
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_alert_test.2920489176
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3412978638
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/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.1549383197
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.303794630
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.3034724626
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1518525987
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.657021145



Total test records in report: 1839
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_override.1983701194 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:53 AM UTC 24 53043128 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3952303915 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:53 AM UTC 24 93003612 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.2025503354 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:54 AM UTC 24 138497740 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.4092283209 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:56 AM UTC 24 595527287 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2320286116 Oct 15 11:40:53 AM UTC 24 Oct 15 11:40:57 AM UTC 24 147360022 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2697852382 Oct 15 11:40:55 AM UTC 24 Oct 15 11:40:58 AM UTC 24 300635615 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.2783320333 Oct 15 11:40:53 AM UTC 24 Oct 15 11:40:58 AM UTC 24 317399568 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2788030808 Oct 15 11:41:19 AM UTC 24 Oct 15 11:41:30 AM UTC 24 6038888446 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.756645858 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:58 AM UTC 24 319534532 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.3142857665 Oct 15 11:40:54 AM UTC 24 Oct 15 11:40:58 AM UTC 24 592937234 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2126370388 Oct 15 11:40:48 AM UTC 24 Oct 15 11:40:59 AM UTC 24 194684416 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_alert_test.4075884741 Oct 15 11:41:39 AM UTC 24 Oct 15 11:41:41 AM UTC 24 44710823 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.2557224462 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:00 AM UTC 24 3081221868 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3921475636 Oct 15 11:40:48 AM UTC 24 Oct 15 11:41:00 AM UTC 24 1614762038 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1934524997 Oct 15 11:40:55 AM UTC 24 Oct 15 11:41:01 AM UTC 24 993030284 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2649692011 Oct 15 11:40:48 AM UTC 24 Oct 15 11:41:01 AM UTC 24 9399894110 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.3376128517 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:01 AM UTC 24 733887074 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.1506404869 Oct 15 11:40:49 AM UTC 24 Oct 15 11:41:01 AM UTC 24 4855090551 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.38226376 Oct 15 11:40:56 AM UTC 24 Oct 15 11:41:01 AM UTC 24 236024410 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3366734943 Oct 15 11:40:59 AM UTC 24 Oct 15 11:41:02 AM UTC 24 16046446 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_perf.3720225874 Oct 15 11:40:55 AM UTC 24 Oct 15 11:41:02 AM UTC 24 833396560 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_override.1756529895 Oct 15 11:40:59 AM UTC 24 Oct 15 11:41:02 AM UTC 24 29981960 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.955186105 Oct 15 11:40:59 AM UTC 24 Oct 15 11:41:03 AM UTC 24 33657516 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.3837845461 Oct 15 11:41:01 AM UTC 24 Oct 15 11:41:03 AM UTC 24 210514916 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1723546635 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:03 AM UTC 24 4481483444 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.3539450972 Oct 15 11:40:57 AM UTC 24 Oct 15 11:41:03 AM UTC 24 923153991 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.405845637 Oct 15 11:40:55 AM UTC 24 Oct 15 11:41:04 AM UTC 24 4149802163 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.3894521439 Oct 15 11:40:57 AM UTC 24 Oct 15 11:41:04 AM UTC 24 1783848063 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.84412537 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:04 AM UTC 24 2140711055 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2186082410 Oct 15 11:41:18 AM UTC 24 Oct 15 11:41:29 AM UTC 24 570355347 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1770228963 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:05 AM UTC 24 3102016076 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.3538258765 Oct 15 11:41:03 AM UTC 24 Oct 15 11:41:06 AM UTC 24 193811979 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_perf.725859625 Oct 15 11:41:01 AM UTC 24 Oct 15 11:41:42 AM UTC 24 6177617592 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.4176923899 Oct 15 11:41:05 AM UTC 24 Oct 15 11:41:07 AM UTC 24 365234933 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2840012679 Oct 15 11:40:58 AM UTC 24 Oct 15 11:41:07 AM UTC 24 2132395457 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2790303216 Oct 15 11:41:22 AM UTC 24 Oct 15 11:41:42 AM UTC 24 3923535926 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.1060998766 Oct 15 11:41:02 AM UTC 24 Oct 15 11:41:07 AM UTC 24 244691309 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.1941877923 Oct 15 11:41:06 AM UTC 24 Oct 15 11:41:08 AM UTC 24 139881145 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2393115932 Oct 15 11:41:01 AM UTC 24 Oct 15 11:41:09 AM UTC 24 154173602 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.2542771279 Oct 15 11:41:01 AM UTC 24 Oct 15 11:41:11 AM UTC 24 3783675737 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2736645581 Oct 15 11:41:07 AM UTC 24 Oct 15 11:41:12 AM UTC 24 1377217103 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_mode_toggle.3891086339 Oct 15 11:41:08 AM UTC 24 Oct 15 11:41:12 AM UTC 24 74858331 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.2001325135 Oct 15 11:41:08 AM UTC 24 Oct 15 11:41:12 AM UTC 24 1043772516 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.779446731 Oct 15 11:40:53 AM UTC 24 Oct 15 11:41:13 AM UTC 24 24534434934 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.4258558468 Oct 15 11:41:09 AM UTC 24 Oct 15 11:41:13 AM UTC 24 1746158578 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.2838288290 Oct 15 11:41:04 AM UTC 24 Oct 15 11:41:13 AM UTC 24 1211869057 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2769870778 Oct 15 11:40:48 AM UTC 24 Oct 15 11:41:14 AM UTC 24 7359236912 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_perf.2152151455 Oct 15 11:41:06 AM UTC 24 Oct 15 11:41:14 AM UTC 24 751284356 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.1348992602 Oct 15 11:41:12 AM UTC 24 Oct 15 11:41:15 AM UTC 24 425322239 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_alert_test.913194762 Oct 15 11:41:14 AM UTC 24 Oct 15 11:41:16 AM UTC 24 14724561 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_override.2415726236 Oct 15 11:41:14 AM UTC 24 Oct 15 11:41:16 AM UTC 24 89790500 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3942826083 Oct 15 11:41:14 AM UTC 24 Oct 15 11:41:17 AM UTC 24 163285535 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.715546791 Oct 15 11:41:09 AM UTC 24 Oct 15 11:41:17 AM UTC 24 400874392 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.4080667617 Oct 15 11:41:13 AM UTC 24 Oct 15 11:41:17 AM UTC 24 1258780994 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.1883307217 Oct 15 11:41:13 AM UTC 24 Oct 15 11:41:17 AM UTC 24 504984846 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.1011440707 Oct 15 11:41:04 AM UTC 24 Oct 15 11:41:18 AM UTC 24 1296291391 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.2879360912 Oct 15 11:41:26 AM UTC 24 Oct 15 11:41:29 AM UTC 24 659363342 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.4222429215 Oct 15 11:41:13 AM UTC 24 Oct 15 11:41:19 AM UTC 24 500578830 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.3441460406 Oct 15 11:40:55 AM UTC 24 Oct 15 11:41:19 AM UTC 24 633819155 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.2054280598 Oct 15 11:41:17 AM UTC 24 Oct 15 11:41:19 AM UTC 24 172184454 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.2585754105 Oct 15 11:41:02 AM UTC 24 Oct 15 11:41:21 AM UTC 24 3530398411 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.22055875 Oct 15 11:41:03 AM UTC 24 Oct 15 11:41:21 AM UTC 24 13241213743 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.1534141892 Oct 15 11:41:19 AM UTC 24 Oct 15 11:41:29 AM UTC 24 181941749 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.2072419560 Oct 15 11:41:02 AM UTC 24 Oct 15 11:41:22 AM UTC 24 3878502959 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.4171570802 Oct 15 11:41:17 AM UTC 24 Oct 15 11:41:23 AM UTC 24 519592841 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.4097296515 Oct 15 11:41:19 AM UTC 24 Oct 15 11:41:23 AM UTC 24 751192656 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.1008602601 Oct 15 11:41:12 AM UTC 24 Oct 15 11:41:25 AM UTC 24 620083203 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.711426619 Oct 15 11:41:03 AM UTC 24 Oct 15 11:41:25 AM UTC 24 2510942982 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2636783263 Oct 15 11:41:22 AM UTC 24 Oct 15 11:41:25 AM UTC 24 2970975518 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.1168065451 Oct 15 11:41:24 AM UTC 24 Oct 15 11:41:27 AM UTC 24 228353376 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2302608294 Oct 15 11:41:34 AM UTC 24 Oct 15 11:41:40 AM UTC 24 7697376507 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_perf.3431609431 Oct 15 11:41:26 AM UTC 24 Oct 15 11:41:33 AM UTC 24 4908347318 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.1639933529 Oct 15 11:41:23 AM UTC 24 Oct 15 11:41:33 AM UTC 24 858383783 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.2663035128 Oct 15 11:41:38 AM UTC 24 Oct 15 11:41:40 AM UTC 24 36995966 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.3781708727 Oct 15 11:41:33 AM UTC 24 Oct 15 11:41:36 AM UTC 24 692465086 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.1463575234 Oct 15 11:41:28 AM UTC 24 Oct 15 11:41:38 AM UTC 24 3903445117 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2780551912 Oct 15 11:41:23 AM UTC 24 Oct 15 11:41:38 AM UTC 24 3093186057 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.983737173 Oct 15 11:41:33 AM UTC 24 Oct 15 11:41:38 AM UTC 24 904584968 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_mode_toggle.3229760093 Oct 15 11:41:30 AM UTC 24 Oct 15 11:41:39 AM UTC 24 157255831 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.408905815 Oct 15 11:41:34 AM UTC 24 Oct 15 11:41:39 AM UTC 24 465661545 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_override.3529345533 Oct 15 11:41:40 AM UTC 24 Oct 15 11:41:42 AM UTC 24 44367853 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.2316046476 Oct 15 11:41:37 AM UTC 24 Oct 15 11:41:40 AM UTC 24 302247504 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.3367877185 Oct 15 11:41:14 AM UTC 24 Oct 15 11:41:42 AM UTC 24 1407503133 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.1384867999 Oct 15 11:41:37 AM UTC 24 Oct 15 11:41:43 AM UTC 24 484998376 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.849735681 Oct 15 11:41:31 AM UTC 24 Oct 15 11:41:43 AM UTC 24 992351116 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.2585512319 Oct 15 11:41:41 AM UTC 24 Oct 15 11:41:44 AM UTC 24 395980550 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.450679298 Oct 15 11:41:20 AM UTC 24 Oct 15 11:41:49 AM UTC 24 5768400533 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.1055248423 Oct 15 11:41:41 AM UTC 24 Oct 15 11:41:49 AM UTC 24 847496091 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.945471898 Oct 15 11:41:23 AM UTC 24 Oct 15 11:43:04 AM UTC 24 19144452356 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2999921083 Oct 15 11:41:19 AM UTC 24 Oct 15 11:41:50 AM UTC 24 1330695594 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.2255401379 Oct 15 11:40:48 AM UTC 24 Oct 15 11:41:52 AM UTC 24 3161734599 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.3841154515 Oct 15 11:41:44 AM UTC 24 Oct 15 11:41:52 AM UTC 24 366629148 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.4292475250 Oct 15 11:41:41 AM UTC 24 Oct 15 11:41:55 AM UTC 24 1637465708 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.318425426 Oct 15 11:42:52 AM UTC 24 Oct 15 11:43:19 AM UTC 24 2042656094 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.3664383007 Oct 15 11:41:53 AM UTC 24 Oct 15 11:41:56 AM UTC 24 164514453 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.3176083473 Oct 15 11:41:50 AM UTC 24 Oct 15 11:41:57 AM UTC 24 2494450896 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.1198653589 Oct 15 11:41:55 AM UTC 24 Oct 15 11:41:58 AM UTC 24 172257509 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.3479564734 Oct 15 11:41:43 AM UTC 24 Oct 15 11:41:59 AM UTC 24 866763203 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.3797185624 Oct 15 11:40:55 AM UTC 24 Oct 15 11:42:00 AM UTC 24 46197643381 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2790291625 Oct 15 11:41:03 AM UTC 24 Oct 15 11:42:00 AM UTC 24 4774521524 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.2194212277 Oct 15 11:41:50 AM UTC 24 Oct 15 11:42:02 AM UTC 24 4500885921 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.3298728298 Oct 15 11:40:59 AM UTC 24 Oct 15 11:42:04 AM UTC 24 5503256279 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_perf.268903916 Oct 15 11:41:57 AM UTC 24 Oct 15 11:42:04 AM UTC 24 1084238788 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_mode_toggle.1227875692 Oct 15 11:42:01 AM UTC 24 Oct 15 11:42:05 AM UTC 24 231193234 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.1969494846 Oct 15 11:41:01 AM UTC 24 Oct 15 11:42:06 AM UTC 24 8487286233 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.1338689535 Oct 15 11:41:44 AM UTC 24 Oct 15 11:42:07 AM UTC 24 719914941 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.2459409544 Oct 15 11:41:59 AM UTC 24 Oct 15 11:42:08 AM UTC 24 3540361539 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.2912239045 Oct 15 11:41:39 AM UTC 24 Oct 15 11:42:08 AM UTC 24 6631365686 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.3164698549 Oct 15 11:42:05 AM UTC 24 Oct 15 11:42:09 AM UTC 24 176462787 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_perf.573507112 Oct 15 11:43:19 AM UTC 24 Oct 15 11:43:24 AM UTC 24 437550821 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.2282842792 Oct 15 11:42:05 AM UTC 24 Oct 15 11:42:10 AM UTC 24 165130797 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.3770066978 Oct 15 11:42:06 AM UTC 24 Oct 15 11:42:11 AM UTC 24 1038231226 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.3117436300 Oct 15 11:42:03 AM UTC 24 Oct 15 11:42:12 AM UTC 24 437636138 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.1031249255 Oct 15 11:42:09 AM UTC 24 Oct 15 11:42:12 AM UTC 24 63805882 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2794299764 Oct 15 11:42:05 AM UTC 24 Oct 15 11:42:12 AM UTC 24 6396417102 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_alert_test.3049786891 Oct 15 11:42:11 AM UTC 24 Oct 15 11:42:13 AM UTC 24 37853147 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.4249207688 Oct 15 11:42:08 AM UTC 24 Oct 15 11:42:13 AM UTC 24 479097328 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_override.1810254942 Oct 15 11:42:12 AM UTC 24 Oct 15 11:42:14 AM UTC 24 157476104 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.2095230532 Oct 15 11:42:09 AM UTC 24 Oct 15 11:42:14 AM UTC 24 533732879 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.726843996 Oct 15 11:40:59 AM UTC 24 Oct 15 11:43:13 AM UTC 24 11038616954 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3741783091 Oct 15 11:41:43 AM UTC 24 Oct 15 11:42:15 AM UTC 24 1199003454 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3117490277 Oct 15 11:41:15 AM UTC 24 Oct 15 11:42:15 AM UTC 24 2088144273 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.1182022796 Oct 15 11:42:13 AM UTC 24 Oct 15 11:42:16 AM UTC 24 334461662 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.785491365 Oct 15 11:41:26 AM UTC 24 Oct 15 11:42:18 AM UTC 24 8068555740 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.1257662232 Oct 15 11:42:15 AM UTC 24 Oct 15 11:42:20 AM UTC 24 294987154 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.1025194677 Oct 15 11:41:49 AM UTC 24 Oct 15 11:42:22 AM UTC 24 4689565896 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.1419709280 Oct 15 11:42:15 AM UTC 24 Oct 15 11:42:25 AM UTC 24 152511283 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.2431903058 Oct 15 11:41:01 AM UTC 24 Oct 15 11:42:29 AM UTC 24 5600905781 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.2557909720 Oct 15 11:41:04 AM UTC 24 Oct 15 11:42:30 AM UTC 24 8711186144 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.2086456157 Oct 15 11:42:14 AM UTC 24 Oct 15 11:42:31 AM UTC 24 244639614 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.3669034559 Oct 15 11:42:30 AM UTC 24 Oct 15 11:42:34 AM UTC 24 278051742 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.3103863813 Oct 15 11:42:23 AM UTC 24 Oct 15 11:42:34 AM UTC 24 1016914148 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.3079411177 Oct 15 11:42:14 AM UTC 24 Oct 15 11:42:35 AM UTC 24 664657505 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.3629550448 Oct 15 11:42:32 AM UTC 24 Oct 15 11:42:36 AM UTC 24 495067256 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.3907140395 Oct 15 11:42:16 AM UTC 24 Oct 15 11:42:37 AM UTC 24 1270530023 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.2775022204 Oct 15 11:42:15 AM UTC 24 Oct 15 11:42:38 AM UTC 24 829317151 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.2871621745 Oct 15 11:42:29 AM UTC 24 Oct 15 11:42:43 AM UTC 24 3313489339 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3100461525 Oct 15 11:41:06 AM UTC 24 Oct 15 11:43:16 AM UTC 24 19940897262 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.4242820959 Oct 15 11:41:02 AM UTC 24 Oct 15 11:42:44 AM UTC 24 24404564455 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.1705944105 Oct 15 11:42:35 AM UTC 24 Oct 15 11:42:45 AM UTC 24 3723307330 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1131578098 Oct 15 11:42:34 AM UTC 24 Oct 15 11:42:45 AM UTC 24 1544388186 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2740842546 Oct 15 11:42:19 AM UTC 24 Oct 15 11:42:45 AM UTC 24 4742670171 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.1072938067 Oct 15 11:42:43 AM UTC 24 Oct 15 11:42:46 AM UTC 24 47979522 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.1868609550 Oct 15 11:42:42 AM UTC 24 Oct 15 11:42:46 AM UTC 24 1432368484 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.230311117 Oct 15 11:41:40 AM UTC 24 Oct 15 11:42:47 AM UTC 24 9837816299 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.4163682699 Oct 15 11:42:12 AM UTC 24 Oct 15 11:42:48 AM UTC 24 7978419480 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.1548694152 Oct 15 11:42:45 AM UTC 24 Oct 15 11:42:48 AM UTC 24 428376240 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.1990790980 Oct 15 11:42:38 AM UTC 24 Oct 15 11:42:48 AM UTC 24 1528335272 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.838679482 Oct 15 11:42:46 AM UTC 24 Oct 15 11:42:48 AM UTC 24 226016360 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.803254186 Oct 15 11:42:47 AM UTC 24 Oct 15 11:43:15 AM UTC 24 1779970096 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.3103088445 Oct 15 11:42:46 AM UTC 24 Oct 15 11:42:49 AM UTC 24 586251906 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_alert_test.3403582483 Oct 15 11:42:47 AM UTC 24 Oct 15 11:42:49 AM UTC 24 56804941 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_override.2922069644 Oct 15 11:42:48 AM UTC 24 Oct 15 11:42:50 AM UTC 24 37557623 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.1545308948 Oct 15 11:42:45 AM UTC 24 Oct 15 11:42:51 AM UTC 24 508807823 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.1817168341 Oct 15 11:42:46 AM UTC 24 Oct 15 11:42:51 AM UTC 24 473214909 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2302377736 Oct 15 11:42:45 AM UTC 24 Oct 15 11:42:51 AM UTC 24 255990643 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.3580262921 Oct 15 11:42:49 AM UTC 24 Oct 15 11:42:52 AM UTC 24 229660414 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.3517014847 Oct 15 11:40:48 AM UTC 24 Oct 15 11:42:53 AM UTC 24 2485406974 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.2487381662 Oct 15 11:42:52 AM UTC 24 Oct 15 11:42:55 AM UTC 24 76284517 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.501591977 Oct 15 11:40:48 AM UTC 24 Oct 15 11:42:56 AM UTC 24 8078564621 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1566622756 Oct 15 11:42:57 AM UTC 24 Oct 15 11:43:02 AM UTC 24 520160417 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.4007358909 Oct 15 11:42:49 AM UTC 24 Oct 15 11:43:02 AM UTC 24 683451304 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.1794897589 Oct 15 11:43:20 AM UTC 24 Oct 15 11:43:25 AM UTC 24 464159728 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.3939829726 Oct 15 11:43:04 AM UTC 24 Oct 15 11:43:17 AM UTC 24 5682319157 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.4278277813 Oct 15 11:42:50 AM UTC 24 Oct 15 11:43:18 AM UTC 24 6571019816 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.225370565 Oct 15 11:43:17 AM UTC 24 Oct 15 11:43:20 AM UTC 24 643032641 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.2503559282 Oct 15 11:42:58 AM UTC 24 Oct 15 11:43:20 AM UTC 24 1414255578 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.1572616822 Oct 15 11:43:17 AM UTC 24 Oct 15 11:43:20 AM UTC 24 404890028 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2708140656 Oct 15 11:43:06 AM UTC 24 Oct 15 11:43:20 AM UTC 24 5517291394 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.2319102333 Oct 15 11:43:30 AM UTC 24 Oct 15 11:44:52 AM UTC 24 3558006652 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.1195639492 Oct 15 11:42:53 AM UTC 24 Oct 15 11:43:23 AM UTC 24 1500303742 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.1596406279 Oct 15 11:41:42 AM UTC 24 Oct 15 11:43:24 AM UTC 24 8448454552 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.2534467538 Oct 15 11:43:22 AM UTC 24 Oct 15 11:43:25 AM UTC 24 557963736 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2719888883 Oct 15 11:43:19 AM UTC 24 Oct 15 11:43:26 AM UTC 24 693702492 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.349790780 Oct 15 11:43:24 AM UTC 24 Oct 15 11:43:26 AM UTC 24 198508752 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.2280699629 Oct 15 11:44:43 AM UTC 24 Oct 15 11:44:51 AM UTC 24 4094553178 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.3633027386 Oct 15 11:42:49 AM UTC 24 Oct 15 11:43:28 AM UTC 24 535998746 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_alert_test.3816733294 Oct 15 11:43:27 AM UTC 24 Oct 15 11:43:29 AM UTC 24 46779281 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.2265947940 Oct 15 11:43:26 AM UTC 24 Oct 15 11:43:29 AM UTC 24 126563337 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.4287729259 Oct 15 11:43:25 AM UTC 24 Oct 15 11:43:30 AM UTC 24 1701027673 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.761129141 Oct 15 11:43:25 AM UTC 24 Oct 15 11:43:30 AM UTC 24 1641990112 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_override.787300718 Oct 15 11:43:28 AM UTC 24 Oct 15 11:43:30 AM UTC 24 47061695 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.3660410897 Oct 15 11:43:26 AM UTC 24 Oct 15 11:43:31 AM UTC 24 811020845 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.1325733337 Oct 15 11:43:21 AM UTC 24 Oct 15 11:43:31 AM UTC 24 403085454 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.3704883328 Oct 15 11:43:24 AM UTC 24 Oct 15 11:43:33 AM UTC 24 336405212 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.3332027771 Oct 15 11:43:31 AM UTC 24 Oct 15 11:43:33 AM UTC 24 380811944 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1715407277 Oct 15 11:43:34 AM UTC 24 Oct 15 11:43:36 AM UTC 24 144954098 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3283916271 Oct 15 11:43:04 AM UTC 24 Oct 15 11:43:39 AM UTC 24 15499391798 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.1042453316 Oct 15 11:43:32 AM UTC 24 Oct 15 11:43:40 AM UTC 24 217530935 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.475829936 Oct 15 11:43:35 AM UTC 24 Oct 15 11:43:42 AM UTC 24 128336202 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.4264463442 Oct 15 11:41:50 AM UTC 24 Oct 15 11:43:42 AM UTC 24 2808162245 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.2433308010 Oct 15 11:43:32 AM UTC 24 Oct 15 11:43:46 AM UTC 24 740124123 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.953594377 Oct 15 11:43:42 AM UTC 24 Oct 15 11:43:50 AM UTC 24 2245737483 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.503216044 Oct 15 11:43:34 AM UTC 24 Oct 15 11:43:51 AM UTC 24 3928474594 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.3871885536 Oct 15 11:43:40 AM UTC 24 Oct 15 11:43:52 AM UTC 24 3156044220 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.2726790085 Oct 15 11:42:14 AM UTC 24 Oct 15 11:43:55 AM UTC 24 40697035845 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_override.1753985503 Oct 15 11:44:55 AM UTC 24 Oct 15 11:44:58 AM UTC 24 140229475 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.1237570012 Oct 15 11:43:53 AM UTC 24 Oct 15 11:43:56 AM UTC 24 217971545 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.1886055523 Oct 15 11:43:45 AM UTC 24 Oct 15 11:43:58 AM UTC 24 4467915905 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3808789906 Oct 15 11:43:42 AM UTC 24 Oct 15 11:43:59 AM UTC 24 706893204 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.3871407982 Oct 15 11:43:51 AM UTC 24 Oct 15 11:44:00 AM UTC 24 1583946125 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.4163567683 Oct 15 11:43:56 AM UTC 24 Oct 15 11:44:00 AM UTC 24 257477400 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1450273608 Oct 15 11:43:57 AM UTC 24 Oct 15 11:44:04 AM UTC 24 431909776 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.3256305941 Oct 15 11:43:27 AM UTC 24 Oct 15 11:44:05 AM UTC 24 1988173639 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_hrst.3094766132 Oct 15 11:44:00 AM UTC 24 Oct 15 11:44:05 AM UTC 24 913437032 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.2753003756 Oct 15 11:42:13 AM UTC 24 Oct 15 11:44:07 AM UTC 24 20744124590 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.202624411 Oct 15 11:44:04 AM UTC 24 Oct 15 11:44:07 AM UTC 24 192129246 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.2824113186 Oct 15 11:43:59 AM UTC 24 Oct 15 11:44:08 AM UTC 24 3686535951 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1809015039 Oct 15 11:44:07 AM UTC 24 Oct 15 11:44:11 AM UTC 24 143794304 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.2201547170 Oct 15 11:44:08 AM UTC 24 Oct 15 11:44:12 AM UTC 24 73240397 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1497229590 Oct 15 11:44:06 AM UTC 24 Oct 15 11:44:13 AM UTC 24 1522807253 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.2085337734 Oct 15 11:44:31 AM UTC 24 Oct 15 11:44:46 AM UTC 24 5557160926 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3181736969 Oct 15 11:42:18 AM UTC 24 Oct 15 11:44:13 AM UTC 24 39420997602 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.804061801 Oct 15 11:44:50 AM UTC 24 Oct 15 11:44:55 AM UTC 24 952193057 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.394520858 Oct 15 11:44:09 AM UTC 24 Oct 15 11:44:14 AM UTC 24 498599325 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.664079940 Oct 15 11:43:47 AM UTC 24 Oct 15 11:44:14 AM UTC 24 11484296143 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.4088094416 Oct 15 11:44:06 AM UTC 24 Oct 15 11:44:15 AM UTC 24 371015098 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_alert_test.3138193750 Oct 15 11:44:14 AM UTC 24 Oct 15 11:44:16 AM UTC 24 196964302 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.854474508 Oct 15 11:44:12 AM UTC 24 Oct 15 11:44:16 AM UTC 24 702241827 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_override.4064910929 Oct 15 11:44:15 AM UTC 24 Oct 15 11:44:17 AM UTC 24 71736237 ps
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T375 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.4260516667 Oct 15 11:41:50 AM UTC 24 Oct 15 11:44:22 AM UTC 24 14774963043 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.4222202145 Oct 15 11:44:21 AM UTC 24 Oct 15 11:44:23 AM UTC 24 339671831 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_alert_test.1058397385 Oct 15 11:44:53 AM UTC 24 Oct 15 11:44:55 AM UTC 24 18529040 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.131375979 Oct 15 11:43:40 AM UTC 24 Oct 15 11:44:25 AM UTC 24 12224888253 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_perf.1483380310 Oct 15 11:44:41 AM UTC 24 Oct 15 11:44:48 AM UTC 24 2179544912 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.488360184 Oct 15 11:44:18 AM UTC 24 Oct 15 11:44:26 AM UTC 24 711683959 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.1623356774 Oct 15 11:44:23 AM UTC 24 Oct 15 11:44:27 AM UTC 24 149363998 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1883732074 Oct 15 11:42:49 AM UTC 24 Oct 15 11:44:27 AM UTC 24 2237961279 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.786718970 Oct 15 11:43:32 AM UTC 24 Oct 15 11:44:28 AM UTC 24 2078297810 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.227470969 Oct 15 11:42:26 AM UTC 24 Oct 15 11:44:29 AM UTC 24 12754460160 ps
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T191 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2790027049 Oct 15 11:42:49 AM UTC 24 Oct 15 11:44:39 AM UTC 24 1760028115 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.2531433292 Oct 15 11:44:30 AM UTC 24 Oct 15 11:44:39 AM UTC 24 2610869725 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.1182759129 Oct 15 11:44:17 AM UTC 24 Oct 15 11:44:41 AM UTC 24 354948076 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.1708864429 Oct 15 11:42:13 AM UTC 24 Oct 15 11:44:41 AM UTC 24 2239990470 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.2513081903 Oct 15 11:41:18 AM UTC 24 Oct 15 11:44:42 AM UTC 24 3125204793 ps
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T387 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.569203610 Oct 15 11:44:26 AM UTC 24 Oct 15 11:44:43 AM UTC 24 4031694078 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.1947376773 Oct 15 11:44:14 AM UTC 24 Oct 15 11:44:43 AM UTC 24 3526501574 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.2203629064 Oct 15 11:44:41 AM UTC 24 Oct 15 11:44:44 AM UTC 24 399933510 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.1484514516 Oct 15 11:44:41 AM UTC 24 Oct 15 11:44:44 AM UTC 24 157423903 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.3300304245 Oct 15 11:41:15 AM UTC 24 Oct 15 11:44:52 AM UTC 24 17622563717 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.1649772024 Oct 15 11:44:49 AM UTC 24 Oct 15 11:44:53 AM UTC 24 2631079494 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.670032720 Oct 15 11:44:47 AM UTC 24 Oct 15 11:44:53 AM UTC 24 538650795 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.1334501561 Oct 15 11:44:49 AM UTC 24 Oct 15 11:44:54 AM UTC 24 202363989 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1899402782 Oct 15 11:44:23 AM UTC 24 Oct 15 11:44:55 AM UTC 24 744246531 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.3699144824 Oct 15 11:44:53 AM UTC 24 Oct 15 11:44:56 AM UTC 24 146968019 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.1871036948 Oct 15 11:44:53 AM UTC 24 Oct 15 11:44:59 AM UTC 24 2128631483 ps
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