Group : i2c_env_pkg::i2c_fifo_reset_cg
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Group : i2c_env_pkg::i2c_fifo_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
81.82 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 20 2 18 90.00
Crosses 24 6 18 75.00


Variables for Group i2c_env_pkg::i2c_fifo_reset_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acq_overflow 2 1 1 50.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acqrst 2 0 2 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmtrst 2 0 2 100.00 100 1 1 2
cp_rx_overflow 2 1 1 50.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rxrst 2 0 2 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_txrst 2 0 2 100.00 100 1 1 2


Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cp_fmt_threshold_cross 4 0 4 100.00 100 1 1 0
cp_rx_threshold_cross 4 1 3 75.00 100 1 1 0
cp_acq_threshold_cross 4 1 3 75.00 100 1 1 0
cp_rx_overflow_cross 4 2 2 50.00 100 1 1 0
cp_acq_overflow_cross 4 2 2 50.00 100 1 1 0
cp_tx_threshold_cross 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_acq_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3645 1 T1 1 T2 15 T3 1


Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3643 1 T1 1 T2 15 T3 1
auto[1] 2 1 T233 2 - - - -


Summary for Variable cp_acqrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acqrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 798 1 T2 14 T44 1 T37 16
auto[1] 2847 1 T1 1 T2 1 T3 1


Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2968 1 T1 1 T2 15 T3 1
auto[1] 677 1 T9 2 T44 2 T234 2


Summary for Variable cp_fmtrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmtrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 595 1 T2 7 T9 2 T44 2
auto[1] 3050 1 T1 1 T2 8 T3 1


Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_rx_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3645 1 T1 1 T2 15 T3 1


Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3625 1 T1 1 T2 15 T3 1
auto[1] 20 1 T78 1 T235 1 T236 1


Summary for Variable cp_rxrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 927 1 T2 14 T9 2 T44 2
auto[1] 2718 1 T1 1 T2 1 T3 1


Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3021 1 T1 1 T2 15 T3 1
auto[1] 624 1 T44 1 T234 2 T237 2


Summary for Variable cp_txrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 798 1 T2 14 T9 1 T37 16
auto[1] 2847 1 T1 1 T2 1 T3 1


Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins
cp_fmt_threshold   cp_fmtrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 353 1 T2 7 T37 8 T38 5
auto[0] auto[1] 2615 1 T1 1 T2 8 T3 1
auto[1] auto[0] 242 1 T9 2 T44 2 T234 2
auto[1] auto[1] 435 1 T75 10 T238 9 T59 7


Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_rx_threshold_cross

Uncovered bins
cp_rx_thresholdcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_rx_threshold   cp_rxrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 927 1 T2 14 T9 2 T44 2
auto[0] auto[1] 2698 1 T1 1 T2 1 T3 1
auto[1] auto[1] 20 1 T78 1 T235 1 T236 1


Summary for Cross cp_acq_threshold_cross

Samples crossed: cp_acq_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_acq_threshold_cross

Uncovered bins
cp_acq_thresholdcp_fmtrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_acq_threshold   cp_fmtrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 593 1 T2 7 T9 2 T44 2
auto[0] auto[1] 3050 1 T1 1 T2 8 T3 1
auto[1] auto[0] 2 1 T233 2 - - - -


Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes
cp_rx_overflowcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_rx_overflow   cp_rxrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 927 1 T2 14 T9 2 T44 2
auto[0] auto[1] 2718 1 T1 1 T2 1 T3 1


Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_acq_overflow_cross

Element holes
cp_acq_overflowcp_acqrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_acq_overflow   cp_acqrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 798 1 T2 14 T44 1 T37 16
auto[0] auto[1] 2847 1 T1 1 T2 1 T3 1


Summary for Cross cp_tx_threshold_cross

Samples crossed: cp_tx_threshold cp_txrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_tx_threshold_cross

Bins
cp_tx_threshold   cp_txrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 723 1 T2 14 T9 1 T37 16
auto[0] auto[1] 2298 1 T1 1 T2 1 T3 1
auto[1] auto[0] 75 1 T234 1 T78 2 T239 1
auto[1] auto[1] 549 1 T44 1 T234 1 T237 2