Group : i2c_env_pkg::i2c_scl_stretch_cg
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Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acq_fifo_size 2 0 2 100.00 100 1 1 0
cp_host_mode_stretch 1 0 1 100.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 0 1 100.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_acq_fifo_size

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_empty 111419303 1 T6 60 T9 2192 T10 4079
empty 64742965 1 T3 12802 T4 18112 T5 28708


Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stretch 43328016 1 T3 12802 T4 18112 T5 20918


Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_target_scl_stretch_addr_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
addr_write_byte_stretch 544327 1 T52 336 T63 42 T64 29


Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_empty 5383761 1 T9 1869 T10 3897 T44 269
empty 170839502 1 T3 12802 T4 18112 T5 28708


Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins
cp_acq_fifo_size   cp_tx_fifo_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
empty not_empty 1715 1 T69 7 T70 21 T292 13
empty empty 329466 1 T9 123 T45 194 T72 1972


User Defined Cross Bins for cp_target_scl_stretch_read

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
read_byte_stretch 311377 1 T6 60 T9 323 T10 182
scl_stretch_read_request 5692837 1 T6 60 T9 2192 T10 4079