Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	838973	1			T1	1		T2	2		T3	12
all_pins[1]	838973	1			T1	1		T2	2		T3	12
all_pins[2]	838973	1			T1	1		T2	2		T3	12
all_pins[3]	838973	1			T1	1		T2	2		T3	12
all_pins[4]	838973	1			T1	1		T2	2		T3	12
all_pins[5]	838973	1			T1	1		T2	2		T3	12
all_pins[6]	838973	1			T1	1		T2	2		T3	12
all_pins[7]	838973	1			T1	1		T2	2		T3	12
all_pins[8]	838973	1			T1	1		T2	2		T3	12
all_pins[9]	838973	1			T1	1		T2	2		T3	12
all_pins[10]	838973	1			T1	1		T2	2		T3	12
all_pins[11]	838973	1			T1	1		T2	2		T3	12
all_pins[12]	838973	1			T1	1		T2	2		T3	12
all_pins[13]	838973	1			T1	1		T2	2		T3	12
all_pins[14]	838973	1			T1	1		T2	2		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10398104	1			T1	15		T2	30		T3	160
values[0x1]	2186491	1			T3	20		T5	4		T6	9
transitions[0x0=>0x1]	2185909	1			T3	20		T5	4		T6	9
transitions[0x1=>0x0]	2184614	1			T3	19		T5	3		T6	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	139525	1			T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	699448	1			T3	10		T5	2		T6	4
all_pins[0]	transitions[0x0=>0x1]	699146	1			T3	10		T5	2		T6	4
all_pins[0]	transitions[0x1=>0x0]	56	1			T198	1		T199	1		T20	1
all_pins[1]	values[0x0]	838615	1			T1	1		T2	2		T3	12
all_pins[1]	values[0x1]	358	1			T31	2		T152	42		T271	1
all_pins[1]	transitions[0x0=>0x1]	347	1			T31	2		T152	42		T271	1
all_pins[1]	transitions[0x1=>0x0]	103	1			T49	1		T276	1		T95	1
all_pins[2]	values[0x0]	838859	1			T1	1		T2	2		T3	12
all_pins[2]	values[0x1]	114	1			T49	1		T276	1		T95	1
all_pins[2]	transitions[0x0=>0x1]	104	1			T49	1		T276	1		T95	1
all_pins[2]	transitions[0x1=>0x0]	72	1			T198	2		T199	3		T244	1
all_pins[3]	values[0x0]	838891	1			T1	1		T2	2		T3	12
all_pins[3]	values[0x1]	82	1			T198	4		T199	3		T244	1
all_pins[3]	transitions[0x0=>0x1]	66	1			T198	4		T199	1		T244	1
all_pins[3]	transitions[0x1=>0x0]	80	1			T11	2		T267	1		T272	1
all_pins[4]	values[0x0]	838877	1			T1	1		T2	2		T3	12
all_pins[4]	values[0x1]	96	1			T11	2		T267	1		T272	1
all_pins[4]	transitions[0x0=>0x1]	76	1			T11	2		T267	1		T272	1
all_pins[4]	transitions[0x1=>0x0]	85	1			T198	3		T199	1		T244	2
all_pins[5]	values[0x0]	838868	1			T1	1		T2	2		T3	12
all_pins[5]	values[0x1]	105	1			T198	3		T199	3		T244	2
all_pins[5]	transitions[0x0=>0x1]	92	1			T198	3		T199	3		T244	2
all_pins[5]	transitions[0x1=>0x0]	69	1			T198	2		T199	3		T20	3
all_pins[6]	values[0x0]	838891	1			T1	1		T2	2		T3	12
all_pins[6]	values[0x1]	82	1			T198	2		T199	3		T20	3
all_pins[6]	transitions[0x0=>0x1]	61	1			T199	2		T20	2		T243	1
all_pins[6]	transitions[0x1=>0x0]	33317	1			T8	4		T9	1		T24	14
all_pins[7]	values[0x0]	805635	1			T1	1		T2	2		T3	12
all_pins[7]	values[0x1]	33338	1			T8	4		T9	1		T24	14
all_pins[7]	transitions[0x0=>0x1]	33322	1			T8	4		T9	1		T24	14
all_pins[7]	transitions[0x1=>0x0]	53	1			T198	1		T199	3		T244	2
all_pins[8]	values[0x0]	838904	1			T1	1		T2	2		T3	12
all_pins[8]	values[0x1]	69	1			T198	2		T199	3		T244	2
all_pins[8]	transitions[0x0=>0x1]	45	1			T198	1		T199	1		T244	2
all_pins[8]	transitions[0x1=>0x0]	620125	1			T6	1		T8	2		T9	1
all_pins[9]	values[0x0]	218824	1			T1	1		T2	2		T3	12
all_pins[9]	values[0x1]	620149	1			T6	1		T8	2		T9	1
all_pins[9]	transitions[0x0=>0x1]	620128	1			T6	1		T8	2		T9	1
all_pins[9]	transitions[0x1=>0x0]	62	1			T198	2		T199	3		T20	1
all_pins[10]	values[0x0]	838890	1			T1	1		T2	2		T3	12
all_pins[10]	values[0x1]	83	1			T198	4		T199	4		T20	2
all_pins[10]	transitions[0x0=>0x1]	57	1			T198	1		T199	3		T20	1
all_pins[10]	transitions[0x1=>0x0]	832243	1			T3	10		T5	2		T6	4
all_pins[11]	values[0x0]	6704	1			T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	832269	1			T3	10		T5	2		T6	4
all_pins[11]	transitions[0x0=>0x1]	832235	1			T3	10		T5	2		T6	4
all_pins[11]	transitions[0x1=>0x0]	93	1			T65	1		T70	1		T71	1
all_pins[12]	values[0x0]	838846	1			T1	1		T2	2		T3	12
all_pins[12]	values[0x1]	127	1			T49	1		T65	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	107	1			T49	1		T65	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	65	1			T198	1		T199	3		T244	2
all_pins[13]	values[0x0]	838888	1			T1	1		T2	2		T3	12
all_pins[13]	values[0x1]	85	1			T198	2		T199	5		T244	2
all_pins[13]	transitions[0x0=>0x1]	67	1			T198	2		T199	4		T244	2
all_pins[13]	transitions[0x1=>0x0]	68	1			T198	2		T199	2		T20	2
all_pins[14]	values[0x0]	838887	1			T1	1		T2	2		T3	12
all_pins[14]	values[0x1]	86	1			T198	2		T199	3		T20	2
all_pins[14]	transitions[0x0=>0x1]	56	1			T198	1		T199	3		T20	1
all_pins[14]	transitions[0x1=>0x0]	698123	1			T3	9		T5	1		T6	3