Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] 732188 1 T1 1 T2 2 T3 34
all_pins[1] 732188 1 T1 1 T2 2 T3 34
all_pins[2] 732188 1 T1 1 T2 2 T3 34
all_pins[3] 732188 1 T1 1 T2 2 T3 34
all_pins[4] 732188 1 T1 1 T2 2 T3 34
all_pins[5] 732188 1 T1 1 T2 2 T3 34
all_pins[6] 732188 1 T1 1 T2 2 T3 34
all_pins[7] 732188 1 T1 1 T2 2 T3 34
all_pins[8] 732188 1 T1 1 T2 2 T3 34
all_pins[9] 732188 1 T1 1 T2 2 T3 34
all_pins[10] 732188 1 T1 1 T2 2 T3 34
all_pins[11] 732188 1 T1 1 T2 2 T3 34
all_pins[12] 732188 1 T1 1 T2 2 T3 34
all_pins[13] 732188 1 T1 1 T2 2 T3 34
all_pins[14] 732188 1 T1 1 T2 2 T3 34


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x0] 9042443 1 T1 15 T2 30 T3 442
values[0x1] 1940377 1 T3 68 T4 6 T5 6
transitions[0x0=>0x1] 1939699 1 T3 68 T4 6 T5 6
transitions[0x1=>0x0] 1938394 1 T3 67 T4 5 T5 5


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pin   cp_intr_pin_value   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] values[0x0] 113966 1 T1 1 T2 2 T3 4
all_pins[0] values[0x1] 618222 1 T3 30 T4 2 T5 2
all_pins[0] transitions[0x0=>0x1] 617844 1 T3 30 T4 2 T5 2
all_pins[0] transitions[0x1=>0x0] 69 1 T23 2 T111 1 T272 1
all_pins[1] values[0x0] 731741 1 T1 1 T2 2 T3 34
all_pins[1] values[0x1] 447 1 T26 2 T263 58 T264 6
all_pins[1] transitions[0x0=>0x1] 428 1 T26 2 T263 58 T264 6
all_pins[1] transitions[0x1=>0x0] 98 1 T162 1 T265 1 T273 1
all_pins[2] values[0x0] 732071 1 T1 1 T2 2 T3 34
all_pins[2] values[0x1] 117 1 T162 1 T265 1 T273 1
all_pins[2] transitions[0x0=>0x1] 104 1 T162 1 T265 1 T273 1
all_pins[2] transitions[0x1=>0x0] 70 1 T23 3 T111 3 T180 2
all_pins[3] values[0x0] 732105 1 T1 1 T2 2 T3 34
all_pins[3] values[0x1] 83 1 T23 3 T111 4 T180 2
all_pins[3] transitions[0x0=>0x1] 65 1 T23 3 T111 2 T180 2
all_pins[3] transitions[0x1=>0x0] 86 1 T11 1 T245 3 T23 2
all_pins[4] values[0x0] 732084 1 T1 1 T2 2 T3 34
all_pins[4] values[0x1] 104 1 T11 1 T245 3 T23 2
all_pins[4] transitions[0x0=>0x1] 87 1 T11 1 T245 3 T23 1
all_pins[4] transitions[0x1=>0x0] 59 1 T23 3 T111 3 T115 1
all_pins[5] values[0x0] 732112 1 T1 1 T2 2 T3 34
all_pins[5] values[0x1] 76 1 T23 4 T111 3 T115 1
all_pins[5] transitions[0x0=>0x1] 52 1 T23 1 T111 2 T115 1
all_pins[5] transitions[0x1=>0x0] 65 1 T23 1 T111 5 T180 2
all_pins[6] values[0x0] 732099 1 T1 1 T2 2 T3 34
all_pins[6] values[0x1] 89 1 T23 4 T111 6 T180 2
all_pins[6] transitions[0x0=>0x1] 66 1 T23 4 T111 3 T180 2
all_pins[6] transitions[0x1=>0x0] 32644 1 T3 8 T4 1 T5 1
all_pins[7] values[0x0] 699521 1 T1 1 T2 2 T3 26
all_pins[7] values[0x1] 32667 1 T3 8 T4 1 T5 1
all_pins[7] transitions[0x0=>0x1] 32641 1 T3 8 T4 1 T5 1
all_pins[7] transitions[0x1=>0x0] 84 1 T23 2 T111 4 T115 3
all_pins[8] values[0x0] 732078 1 T1 1 T2 2 T3 34
all_pins[8] values[0x1] 110 1 T23 4 T111 6 T115 3
all_pins[8] transitions[0x0=>0x1] 78 1 T23 2 T111 4 T115 3
all_pins[8] transitions[0x1=>0x0] 562980 1 T4 1 T5 1 T9 1
all_pins[9] values[0x0] 169176 1 T1 1 T2 2 T3 34
all_pins[9] values[0x1] 563012 1 T4 1 T5 1 T9 1
all_pins[9] transitions[0x0=>0x1] 562993 1 T4 1 T5 1 T9 1
all_pins[9] transitions[0x1=>0x0] 57 1 T23 2 T111 1 T180 1
all_pins[10] values[0x0] 732112 1 T1 1 T2 2 T3 34
all_pins[10] values[0x1] 76 1 T23 3 T111 4 T180 1
all_pins[10] transitions[0x0=>0x1] 59 1 T23 2 T111 3 T115 2
all_pins[10] transitions[0x1=>0x0] 725070 1 T3 30 T4 2 T5 2
all_pins[11] values[0x0] 7101 1 T1 1 T2 2 T3 4
all_pins[11] values[0x1] 725087 1 T3 30 T4 2 T5 2
all_pins[11] transitions[0x0=>0x1] 725052 1 T3 30 T4 2 T5 2
all_pins[11] transitions[0x1=>0x0] 94 1 T64 1 T65 1 T68 1
all_pins[12] values[0x0] 732059 1 T1 1 T2 2 T3 34
all_pins[12] values[0x1] 129 1 T64 1 T265 1 T65 1
all_pins[12] transitions[0x0=>0x1] 117 1 T64 1 T265 1 T65 1
all_pins[12] transitions[0x1=>0x0] 66 1 T23 2 T111 4 T180 1
all_pins[13] values[0x0] 732110 1 T1 1 T2 2 T3 34
all_pins[13] values[0x1] 78 1 T23 2 T111 4 T180 1
all_pins[13] transitions[0x0=>0x1] 59 1 T23 1 T111 2 T180 1
all_pins[13] transitions[0x1=>0x0] 61 1 T23 2 T111 7 T115 1
all_pins[14] values[0x0] 732108 1 T1 1 T2 2 T3 34
all_pins[14] values[0x1] 80 1 T23 3 T111 9 T115 1
all_pins[14] transitions[0x0=>0x1] 54 1 T23 2 T111 8 T115 1
all_pins[14] transitions[0x1=>0x0] 616891 1 T3 29 T4 1 T5 1