Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361	1			T198	11		T199	18		T20	4
all_values[1]	361	1			T198	11		T199	18		T20	4
all_values[2]	361	1			T198	11		T199	18		T20	4
all_values[3]	361	1			T198	11		T199	18		T20	4
all_values[4]	361	1			T198	11		T199	18		T20	4
all_values[5]	361	1			T198	11		T199	18		T20	4
all_values[6]	361	1			T198	11		T199	18		T20	4
all_values[7]	361	1			T198	11		T199	18		T20	4
all_values[8]	361	1			T198	11		T199	18		T20	4
all_values[9]	361	1			T198	11		T199	18		T20	4
all_values[10]	361	1			T198	11		T199	18		T20	4
all_values[11]	361	1			T198	11		T199	18		T20	4
all_values[12]	361	1			T198	11		T199	18		T20	4
all_values[13]	361	1			T198	11		T199	18		T20	4
all_values[14]	361	1			T198	11		T199	18		T20	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2883

1

T198

68

T199

125

T20

27

auto[1]

2532

1

T198

97

T199

145

T20

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

929

1

T198

18

T199

36

T20

2

auto[1]

4486

1

T198

147

T199

234

T20

58

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3204

1

T198

103

T199

161

T20

31

auto[1]

2211

1

T198

62

T199

109

T20

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1			T199	2		T131	1		T277	1
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T198	2		T199	3		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1			T198	1		T199	2		T278	2
all_values[0]	auto[0]	auto[1]	auto[1]	69	1			T198	3		T199	3		T244	2
all_values[0]	auto[1]	auto[0]	auto[1]	87	1			T198	3		T199	1		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	77	1			T198	2		T199	7		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T199	1		T20	1		T244	4
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T198	3		T199	7		T243	2
all_values[1]	auto[0]	auto[1]	auto[0]	23	1			T199	1		T279	1		T280	2
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T198	3		T199	3		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	65	1			T198	2		T199	2		T243	1
all_values[1]	auto[1]	auto[1]	auto[1]	78	1			T198	3		T199	4		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	33	1			T198	1		T199	1		T245	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T198	2		T199	4		T243	2
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T198	2		T199	1		T244	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T198	2		T199	5		T20	3
all_values[2]	auto[1]	auto[0]	auto[1]	74	1			T198	1		T199	2		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	58	1			T198	3		T199	5		T244	1
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T198	1		T243	1		T245	3
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T198	2		T199	5		T20	2
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T198	1		T245	1		T253	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T198	4		T199	7		T131	1
all_values[3]	auto[1]	auto[0]	auto[1]	82	1			T199	5		T20	1		T244	1
all_values[3]	auto[1]	auto[1]	auto[1]	62	1			T198	3		T199	1		T20	1
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T199	2		T244	2		T245	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T198	2		T199	3		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T198	1		T244	2		T245	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T198	3		T199	4		T245	4
all_values[4]	auto[1]	auto[0]	auto[1]	78	1			T198	4		T199	2		T20	1
all_values[4]	auto[1]	auto[1]	auto[1]	61	1			T198	1		T199	7		T20	1
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T279	1		T281	1		T282	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T198	2		T199	5		T20	1
all_values[5]	auto[0]	auto[1]	auto[0]	24	1			T20	1		T244	1		T278	1
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T198	5		T199	5		T244	1
all_values[5]	auto[1]	auto[0]	auto[1]	79	1			T198	1		T199	6		T20	2
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T198	3		T199	2		T244	2
all_values[6]	auto[0]	auto[0]	auto[0]	43	1			T199	1		T244	1		T130	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T198	2		T199	2		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	17	1			T198	1		T278	1		T277	2
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T198	5		T199	6		T20	1
all_values[6]	auto[1]	auto[0]	auto[1]	84	1			T198	1		T199	7		T20	1
all_values[6]	auto[1]	auto[1]	auto[1]	62	1			T198	2		T199	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T244	2		T243	2		T245	2
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T198	2		T199	6		T244	1
all_values[7]	auto[0]	auto[1]	auto[0]	14	1			T198	1		T131	1		T283	1
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T198	2		T20	1		T245	5
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T198	1		T199	7		T244	1
all_values[7]	auto[1]	auto[1]	auto[1]	76	1			T198	5		T199	5		T20	3
all_values[8]	auto[0]	auto[0]	auto[0]	48	1			T199	6		T244	1		T243	3
all_values[8]	auto[0]	auto[0]	auto[1]	74	1			T198	4		T199	2		T20	1
all_values[8]	auto[0]	auto[1]	auto[0]	33	1			T198	1		T199	2		T243	1
all_values[8]	auto[0]	auto[1]	auto[1]	70	1			T198	3		T199	6		T20	1
all_values[8]	auto[1]	auto[0]	auto[1]	75	1			T198	2		T199	1		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	61	1			T198	1		T199	1		T20	1
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T243	3		T245	1		T131	1
all_values[9]	auto[0]	auto[0]	auto[1]	79	1			T198	7		T199	3		T20	2
all_values[9]	auto[0]	auto[1]	auto[0]	20	1			T243	1		T131	1		T282	2
all_values[9]	auto[0]	auto[1]	auto[1]	71	1			T199	6		T245	2		T130	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T198	1		T199	3		T20	1
all_values[9]	auto[1]	auto[1]	auto[1]	76	1			T198	3		T199	6		T20	1
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T199	1		T243	2		T245	1
all_values[10]	auto[0]	auto[0]	auto[1]	71	1			T198	1		T199	4		T244	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T198	1		T279	2		T281	1
all_values[10]	auto[0]	auto[1]	auto[1]	85	1			T198	5		T199	6		T20	2
all_values[10]	auto[1]	auto[0]	auto[1]	77	1			T198	1		T199	2		T244	1
all_values[10]	auto[1]	auto[1]	auto[1]	75	1			T198	3		T199	5		T20	2
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T130	2		T253	1		T131	1
all_values[11]	auto[0]	auto[0]	auto[1]	69	1			T198	5		T199	4		T20	3
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T278	1		T284	3		T285	1
all_values[11]	auto[0]	auto[1]	auto[1]	86	1			T198	1		T199	3		T244	2
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T198	1		T199	4		T244	2
all_values[11]	auto[1]	auto[1]	auto[1]	71	1			T198	4		T199	7		T20	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1			T280	1		T283	2		T286	1
all_values[12]	auto[0]	auto[0]	auto[1]	87	1			T198	2		T199	5		T20	2
all_values[12]	auto[0]	auto[1]	auto[0]	15	1			T278	2		T287	1		T288	1
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T198	4		T199	7		T245	3
all_values[12]	auto[1]	auto[0]	auto[1]	95	1			T198	3		T199	3		T20	1
all_values[12]	auto[1]	auto[1]	auto[1]	62	1			T198	2		T199	3		T20	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T199	3		T244	1		T243	1
all_values[13]	auto[0]	auto[0]	auto[1]	66	1			T198	3		T199	1		T243	1
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T199	8		T243	1		T278	1
all_values[13]	auto[0]	auto[1]	auto[1]	83	1			T198	4		T199	3		T20	3
all_values[13]	auto[1]	auto[0]	auto[1]	82	1			T199	1		T244	1		T245	1
all_values[13]	auto[1]	auto[1]	auto[1]	69	1			T198	4		T199	2		T20	1
all_values[14]	auto[0]	auto[0]	auto[0]	46	1			T198	4		T199	2		T253	2
all_values[14]	auto[0]	auto[0]	auto[1]	59	1			T198	1		T199	4		T244	3
all_values[14]	auto[0]	auto[1]	auto[0]	30	1			T198	3		T199	3		T278	1
all_values[14]	auto[0]	auto[1]	auto[1]	84	1			T198	1		T199	3		T20	2
all_values[14]	auto[1]	auto[0]	auto[1]	76	1			T198	1		T199	2		T20	1
all_values[14]	auto[1]	auto[1]	auto[1]	66	1			T198	1		T199	4		T20	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal