Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	360	1			T23	11		T111	18		T180	4
all_values[1]	360	1			T23	11		T111	18		T180	4
all_values[2]	360	1			T23	11		T111	18		T180	4
all_values[3]	360	1			T23	11		T111	18		T180	4
all_values[4]	360	1			T23	11		T111	18		T180	4
all_values[5]	360	1			T23	11		T111	18		T180	4
all_values[6]	360	1			T23	11		T111	18		T180	4
all_values[7]	360	1			T23	11		T111	18		T180	4
all_values[8]	360	1			T23	11		T111	18		T180	4
all_values[9]	360	1			T23	11		T111	18		T180	4
all_values[10]	360	1			T23	11		T111	18		T180	4
all_values[11]	360	1			T23	11		T111	18		T180	4
all_values[12]	360	1			T23	11		T111	18		T180	4
all_values[13]	360	1			T23	11		T111	18		T180	4
all_values[14]	360	1			T23	11		T111	18		T180	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2913

1

T23

90

T111

152

T180

24

auto[1]

2487

1

T23

75

T111

118

T180

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

837

1

T23

15

T111

20

T180

17

auto[1]

4563

1

T23

150

T111

250

T180

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3150

1

T23

98

T111

165

T180

39

auto[1]

2250

1

T23

67

T111

105

T180

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1			T115	2		T41	2		T274	1
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T23	2		T111	3		T41	2
all_values[0]	auto[0]	auto[1]	auto[0]	13	1			T23	1		T115	1		T41	1
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T23	1		T111	7		T180	1
all_values[0]	auto[1]	auto[0]	auto[1]	87	1			T23	4		T111	3		T115	1
all_values[0]	auto[1]	auto[1]	auto[1]	71	1			T23	3		T111	5		T180	3
all_values[1]	auto[0]	auto[0]	auto[0]	30	1			T41	1		T275	2		T276	3
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T23	4		T111	10		T115	1
all_values[1]	auto[0]	auto[1]	auto[0]	14	1			T23	1		T180	2		T277	2
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T23	2		T111	3		T180	1
all_values[1]	auto[1]	auto[0]	auto[1]	91	1			T23	1		T111	2		T115	2
all_values[1]	auto[1]	auto[1]	auto[1]	76	1			T23	3		T111	3		T180	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T23	2		T115	1		T276	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T23	3		T111	5		T115	2
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T23	3		T180	1		T115	1
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T23	1		T111	3		T180	2
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T23	1		T111	8		T115	2
all_values[2]	auto[1]	auto[1]	auto[1]	63	1			T23	1		T111	2		T180	1
all_values[3]	auto[0]	auto[0]	auto[0]	44	1			T23	1		T111	1		T41	1
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T23	3		T111	6		T115	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T180	1		T115	2		T278	2
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T23	2		T111	2		T180	2
all_values[3]	auto[1]	auto[0]	auto[1]	77	1			T23	2		T111	8		T41	1
all_values[3]	auto[1]	auto[1]	auto[1]	61	1			T23	3		T111	1		T180	1
all_values[4]	auto[0]	auto[0]	auto[0]	26	1			T41	2		T274	3		T276	1
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T23	5		T111	6		T180	2
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T111	1		T115	1		T274	1
all_values[4]	auto[0]	auto[1]	auto[1]	67	1			T23	1		T111	4		T180	1
all_values[4]	auto[1]	auto[0]	auto[1]	82	1			T23	4		T111	5		T115	3
all_values[4]	auto[1]	auto[1]	auto[1]	70	1			T23	1		T111	2		T180	1
all_values[5]	auto[0]	auto[0]	auto[0]	47	1			T111	4		T41	1		T274	1
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T23	3		T111	5		T180	2
all_values[5]	auto[0]	auto[1]	auto[0]	27	1			T111	3		T180	1		T115	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T23	2		T111	2		T115	1
all_values[5]	auto[1]	auto[0]	auto[1]	70	1			T23	3		T111	2		T115	3
all_values[5]	auto[1]	auto[1]	auto[1]	67	1			T23	3		T111	2		T180	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1			T279	1		T280	1		T281	2
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T23	4		T111	6		T180	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T275	1		T129	4		T279	1
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T23	3		T111	4		T180	1
all_values[6]	auto[1]	auto[0]	auto[1]	87	1			T23	2		T111	2		T180	1
all_values[6]	auto[1]	auto[1]	auto[1]	69	1			T23	2		T111	6		T180	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T180	2		T115	1		T274	1
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T23	2		T111	6		T180	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T111	2		T115	1		T129	2
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T23	3		T111	3		T41	5
all_values[7]	auto[1]	auto[0]	auto[1]	68	1			T23	2		T111	5		T180	1
all_values[7]	auto[1]	auto[1]	auto[1]	71	1			T23	4		T111	2		T41	3
all_values[8]	auto[0]	auto[0]	auto[0]	24	1			T23	3		T111	1		T41	1
all_values[8]	auto[0]	auto[0]	auto[1]	77	1			T23	3		T111	3		T180	1
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T180	2		T278	1		T279	1
all_values[8]	auto[0]	auto[1]	auto[1]	73	1			T23	2		T111	6		T115	2
all_values[8]	auto[1]	auto[0]	auto[1]	85	1			T111	4		T180	1		T115	1
all_values[8]	auto[1]	auto[1]	auto[1]	79	1			T23	3		T111	4		T115	2
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T180	2		T282	1		T277	3
all_values[9]	auto[0]	auto[0]	auto[1]	73	1			T23	3		T111	8		T180	1
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T115	2		T283	2		T280	1
all_values[9]	auto[0]	auto[1]	auto[1]	82	1			T23	2		T111	3		T115	2
all_values[9]	auto[1]	auto[0]	auto[1]	84	1			T23	1		T180	1		T41	6
all_values[9]	auto[1]	auto[1]	auto[1]	64	1			T23	5		T111	7		T115	1
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T274	2		T275	1		T130	1
all_values[10]	auto[0]	auto[0]	auto[1]	84	1			T23	3		T111	8		T115	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T180	1		T115	1		T274	1
all_values[10]	auto[0]	auto[1]	auto[1]	73	1			T23	2		T111	3		T180	2
all_values[10]	auto[1]	auto[0]	auto[1]	81	1			T23	4		T111	3		T41	7
all_values[10]	auto[1]	auto[1]	auto[1]	69	1			T23	2		T111	4		T180	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1			T23	1		T111	1		T115	3
all_values[11]	auto[0]	auto[0]	auto[1]	91	1			T23	1		T111	6		T115	1
all_values[11]	auto[0]	auto[1]	auto[0]	19	1			T23	2		T111	4		T115	1
all_values[11]	auto[0]	auto[1]	auto[1]	71	1			T23	4		T111	4		T180	1
all_values[11]	auto[1]	auto[0]	auto[1]	83	1			T23	2		T111	3		T180	2
all_values[11]	auto[1]	auto[1]	auto[1]	61	1			T23	1		T180	1		T115	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1			T180	1		T274	1		T276	1
all_values[12]	auto[0]	auto[0]	auto[1]	67	1			T23	7		T111	6		T115	1
all_values[12]	auto[0]	auto[1]	auto[0]	28	1			T111	2		T41	1		T283	1
all_values[12]	auto[0]	auto[1]	auto[1]	86	1			T23	2		T111	4		T180	2
all_values[12]	auto[1]	auto[0]	auto[1]	76	1			T23	2		T111	4		T180	1
all_values[12]	auto[1]	auto[1]	auto[1]	73	1			T111	2		T115	1		T41	3
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T282	2		T284	1		T277	2
all_values[13]	auto[0]	auto[0]	auto[1]	75	1			T23	5		T111	6		T180	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1			T130	1		T283	2		T285	2
all_values[13]	auto[0]	auto[1]	auto[1]	78	1			T23	1		T111	5		T41	5
all_values[13]	auto[1]	auto[0]	auto[1]	85	1			T23	3		T111	4		T180	1
all_values[13]	auto[1]	auto[1]	auto[1]	68	1			T23	2		T111	3		T180	2
all_values[14]	auto[0]	auto[0]	auto[0]	30	1			T111	1		T180	2		T129	1
all_values[14]	auto[0]	auto[0]	auto[1]	82	1			T23	4		T111	2		T115	2
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T23	1		T180	2		T275	1
all_values[14]	auto[0]	auto[1]	auto[1]	78	1			T23	3		T111	6		T115	3
all_values[14]	auto[1]	auto[0]	auto[1]	90	1			T111	5		T115	1		T41	8
all_values[14]	auto[1]	auto[1]	auto[1]	59	1			T23	3		T111	4		T115	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal