LINE 3682
EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T5,T6 |
| 1 | 1 | 0 | Covered | T102,T104,T107 |
| 1 | 1 | 1 | Covered | T69,T70,T60 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |