Unified Coverage Report :: Module :: keymgr_ctrl

Module : keymgr_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	100.00	98.06		100.00	100.00	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	97.79	100.00	98.06		100.00	100.00	90.91

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	100.00	98.06		100.00	100.00	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.34	99.70	95.19	96.42	100.00	98.60	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	95.89			95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	97.95			97.95
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	99.32			99.32
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	99.32			99.32
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	96.58			96.58
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	97.26			97.26
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	98.63			98.63
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	100.00			100.00
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	100.00			100.00
u_cnt	100.00			100.00
u_data_en	84.15	97.44	33.33		100.00	90.00	100.00
u_err	94.81	100.00	84.44			100.00
u_hw_sel	100.00	100.00				100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_op_state	100.00	100.00	100.00		100.00	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
TOTAL		184	184	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
ALWAYS	243	3	3	100.00
ALWAYS	246	3	3	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	272	7	7	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
ALWAYS	331	21	21	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
ALWAYS	436	73	73	100.00
ALWAYS	654	4	4	100.00
ALWAYS	662	12	12	100.00
ALWAYS	698	5	5	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
ALWAYS	781	3	3	100.00
CONT_ASSIGN	791	1	1	100.00
ROUTINE	838	1	1	100.00
ALWAYS	880	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
149	1	1
150	1	1
151	1	1
152	1	1
154	1	1
164	1	1
165	1	1
168	1	1
184	1	1
185	1	1
186	1	1
187	1	1
201	1	1
206	1	1
212	1	1
214	1	1
229	1	1
237	1	1
243	3	3
246	1	1
247	1	1
249	1	1
257	1	1
259	1	1
263	2	2
270	1	1
272	1	1
273	1	1
274	1	1
276	1	1
277	1	1
278	1	1
279	1	1
298	16	16
305	1	1
328	1	1
331	1	1
332	1	1
333	1	1
337	1	1
339	1	1
340	1	1
343	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
355		unreachable
357		unreachable
362	1	1
363	1	1
364	1	1
370	1	1
371	1	1
375	1	1
376	1	1
377	1	1
378	1	1
414	1	1
425	1	1
426	1	1
432	1	1
436	1	1
439	1	1
440	1	1
441	1	1
444	1	1
447	1	1
450	1	1
453	1	1
456	1	1
459	1	1
462	1	1
465	1	1
469	1	1
471	1	1
474	1	1
478	1	1
482	1	1
485	1	1
486	1	1
487	1	1
488	1	1
			MISSING_ELSE
494	1	1
495	1	1
497	1	1
498	1	1
			MISSING_ELSE
504	1	1
505	1	1
510	1	1
511		unreachable
512		unreachable
			MISSING_ELSE
518	1	1
519	1	1
520	1	1
527	1	1
530	1	1
531	1	1
533	1	1
534	1	1
535	1	1
536	1	1
537	1	1
538	1	1
			MISSING_ELSE
544	1	1
549	1	1
552	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
			MISSING_ELSE
563	1	1
568	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
576	1	1
			MISSING_ELSE
583	1	1
588	1	1
590	1	1
591	1	1
592	1	1
593	1	1
			MISSING_ELSE
602	1	1
604	1	1
605	1	1
614	1	1
615	1	1
			MISSING_ELSE
626	1	1
627	1	1
629	1	1
630	1	1
			MISSING_ELSE
635	1	1
636	1	1
654	1	1
655	1	1
656	1	1
657	1	1
			MISSING_ELSE
662	1	1
663	1	1
665	1	1
667	1	1
670	1	1
673	1	1
676	1	1
679	1	1
682	1	1
685	1	1
686	1	1
690	1	1
698	1	1
699	1	1
703	1	1
704	1	1
705	1	1
			MISSING_ELSE
736	1	1
742	1	1
773	1	1
781	1	1
782	1	1
784	1	1
791	1	1
838	1	1
880	3	3

---

Cond Coverage for Module : keymgr_ctrl

	Total	Covered	Percent
Conditions	206	202	98.06
Logical	206	202	98.06
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (op_i == OpAdvance)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (op_i == OpGenId)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (op_i == OpGenSwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (op_i == OpGenHwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (op_start_i & adv_op & en_i)
             -----1----   ---2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T39,T40
1	1	1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (op_start_i & gen_hw_op & en_i)
             -----1----   ----2----   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T5,T41
1	1	1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T39,T40

 LINE       168
 SUB-EXPRESSION (op_start_i & dis_op)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T39,T40

 LINE       184
 EXPRESSION (op_req & adv_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (op_req & dis_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T39,T40

 LINE       186
 EXPRESSION (op_req & gen_id_op)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
             ---1--   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       187
 SUB-EXPRESSION (gen_sw_op | gen_hw_op)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       201
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T3,T13,T14

 LINE       201
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T17
1	0	Covered	T1,T2,T3

 LINE       229
 EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T17

 LINE       229
 SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       229
 SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (random_req | disabled | invalid | wipe_req)
             -----1----   ----2---   ---3---   ----4---

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T13,T14,T17
0	0	1	0	Covered	T13,T14,T17
0	1	0	0	Covered	T2,T3,T15
1	0	0	0	Covered	T1,T2,T3

 LINE       259
 EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       263
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       263
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       315
 EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
             --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T13

 LINE       328
 EXPRESSION (op_req ? cnt[0] : '0)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T2,T3,T13

 LINE       371
 SUB-EXPRESSION (adv_op || dis_op)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T13
0	1	Covered	T2,T39,T40
1	0	Covered	T2,T3,T13

 LINE       390
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (op_ack & adv_req & ((~op_err)))
             ---1--   ---2---   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T3,T13,T14

 LINE       426
 EXPRESSION (op_ack & dis_req)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T39,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T39,T40

 LINE       482
 EXPRESSION (op_start_i & ((~advance_sel)))
             -----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       510
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       520
 EXPRESSION (en_i ? StCtrlInit : StCtrlWipe)
             --1-

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (advance_sel ? Creator : Disable)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T13

 LINE       531
 EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
             -----1----   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       531
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T38,T40
1	0	Covered	T1,T3,T13

 LINE       533
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T36,T45,T37
1	0	Covered	T38,T40,T4

 LINE       549
 EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
             -----1-----

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T39,T40,T46

 LINE       549
 SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
                 -----1-----

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T3,T13,T14

 LINE       552
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T13,T14
0	1	Covered	T7,T25,T47
1	0	Covered	T40,T48,T49

 LINE       568
 EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
             -----1-----

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T39,T40,T4

 LINE       568
 SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
                 -----1-----

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T3,T14,T15

 LINE       571
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T13,T14
0	1	Covered	T13,T6,T50
1	0	Covered	T51,T48,T52

 LINE       588
 EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T14,T15
1	Covered	T3,T15,T16

 LINE       588
 SUB-EXPRESSION (disable_sel | advance_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T15
0	1	Covered	T3,T15,T16
1	0	Covered	T53,T39,T54

 LINE       590
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T15
0	1	Covered	T14,T17,T18
1	0	Covered	T53,T39,T54

 LINE       592
 EXPRESSION (adv_state || dis_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T15
0	1	Covered	T55,T56,T57
1	0	Covered	T3,T15,T16

 LINE       629
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T15
0	1	Covered	T33,T9,T34
1	0	Covered	T58,T59,T60

 LINE       703
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
             -----------------------1----------------------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T61,T21

 LINE       736
 SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
                 ----1---   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T61,T21

 LINE       736
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       736
 SUB-EXPRESSION (gen_en_o & ((~gen_op)))
                 ----1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       742
 EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T25,T47

 LINE       742
 SUB-EXPRESSION ((op_ack | op_update) & invalid)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T25,T47

 LINE       742
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T17

 LINE       742
 SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
                 ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T17

 LINE       742
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T15

 LINE       742
 SUB-EXPRESSION ((op_ack | op_update) & disabled)
                 ----------1---------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       742
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION ((op_ack | op_update) & op_err)
                 ----------1---------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T13

 LINE       742
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T2,T3,T13

 LINE       773
 EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
             ----------1---------   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       773
 SUB-EXPRESSION (state_d != state_q)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       791
 EXPRESSION (vld_state_change_q & ((!adv_op)))
             ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       793
 EXPRESSION (disabled | (initialized & ((~en_i))))
             ----1---   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T58,T38
1	0	Covered	T2,T3,T15

 LINE       793
 SUB-EXPRESSION (initialized & ((~en_i)))
                 -----1-----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T58,T38

 LINE       793
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Not Covered

---

FSM Coverage for Module : keymgr_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	19	19	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlCreatorRootKey	538	Covered	T3,T13,T14
StCtrlDisabled	536	Covered	T2,T3,T15
StCtrlEntropyReseed	488	Covered	T1,T2,T3
StCtrlInit	520	Covered	T1,T2,T3
StCtrlInvalid	615	Covered	T13,T14,T17
StCtrlOwnerIntKey	557	Covered	T3,T13,T14
StCtrlOwnerKey	576	Covered	T3,T14,T15
StCtrlRandom	498	Covered	T1,T2,T3
StCtrlReset	473	Covered	T1,T2,T3
StCtrlRootKey	512	Covered	T1,T2,T3
StCtrlWipe	486	Covered	T13,T14,T17

transitions	Line No.	Covered	Tests
StCtrlCreatorRootKey->StCtrlDisabled	555	Covered	T39,T40,T46
StCtrlCreatorRootKey->StCtrlOwnerIntKey	557	Covered	T3,T13,T14
StCtrlCreatorRootKey->StCtrlWipe	553	Covered	T7,T25,T40
StCtrlDisabled->StCtrlWipe	630	Covered	T58,T33,T59
StCtrlEntropyReseed->StCtrlRandom	498	Covered	T1,T2,T3
StCtrlInit->StCtrlCreatorRootKey	538	Covered	T3,T13,T14
StCtrlInit->StCtrlDisabled	536	Covered	T2,T4,T62
StCtrlInit->StCtrlWipe	534	Covered	T38,T40,T4
StCtrlOwnerIntKey->StCtrlDisabled	574	Covered	T39,T40,T4
StCtrlOwnerIntKey->StCtrlOwnerKey	576	Covered	T3,T14,T15
StCtrlOwnerIntKey->StCtrlWipe	572	Covered	T13,T51,T6
StCtrlOwnerKey->StCtrlDisabled	593	Covered	T3,T15,T16
StCtrlOwnerKey->StCtrlWipe	591	Covered	T14,T17,T18
StCtrlRandom->StCtrlRootKey	512	Covered	T1,T2,T3
StCtrlReset->StCtrlEntropyReseed	488	Covered	T1,T2,T3
StCtrlReset->StCtrlWipe	486	Covered	T10,T11,T12
StCtrlRootKey->StCtrlInit	520	Covered	T1,T2,T3
StCtrlRootKey->StCtrlWipe	520	Covered	T42,T43,T44
StCtrlWipe->StCtrlInvalid	615	Covered	T13,T14,T17

---

Branch Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
Branches		92	92	100.00
TERNARY	229	4	4	100.00
TERNARY	259	2	2	100.00
TERNARY	328	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	742	6	6	100.00
TERNARY	263	2	2	100.00
TERNARY	263	2	2	100.00
IF	243	2	2	100.00
IF	246	2	2	100.00
IF	272	2	2	100.00
CASE	337	7	7	100.00
CASE	471	39	39	100.00
IF	654	3	3	100.00
CASE	665	9	9	100.00
IF	699	4	4	100.00
IF	781	2	2	100.00
IF	880	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	229	(wipe_req) ? 
-2-:	229	(random_req) ? 
-3-:	229	(init_o) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T13,T14,T17
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	259	(advance_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	414	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	742	(((op_ack | op_update) & invalid)) ? 
-2-:	742	(((op_ack | op_update) & op_fault_err)) ? 
-3-:	742	(((op_ack | op_update) & disabled)) ? 
-4-:	742	(((op_ack | op_update) & op_err)) ? 
-5-:	742	((op_ack | op_update)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T7,T25,T47
0	1	-	-	-	Covered	T13,T14,T17
0	0	1	-	-	Covered	T2,T3,T15
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T2,T3,T13
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	263	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	243	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	case (update_sel)
-2-:	349	if (root_key_valid_q)
-3-:	371	((adv_op || dis_op)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
KeyUpdateRandom	-	-	Covered	T1,T2,T3
KeyUpdateRoot	1	-	Covered	T2,T3,T13
KeyUpdateRoot	0	-	Covered	T1,T22,T23
KeyUpdateKmac	-	1	Covered	T2,T3,T13
KeyUpdateKmac	-	0	Covered	T2,T3,T13
KeyUpdateWipe	-	-	Covered	T13,T14,T17
default	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	471	case (state_q)
-2-:	485	if (inv_state)
-3-:	487	if (advance_sel)
-4-:	497	if (prng_reseed_ack_i)
-5-:	510	if ((int'(cnt) == (EntropyRounds - 1)))
-6-:	520	(en_i) ? 
-7-:	530	(advance_sel) ? 
-8-:	533	if (((!en_i) || inv_state))
-9-:	535	if (dis_state)
-10-:	537	if (adv_state)
-11-:	549	(disable_sel) ? 
-12-:	549	(advance_sel) ? 
-13-:	552	if (((!en_i) || inv_state))
-14-:	554	if (dis_state)
-15-:	556	if (adv_state)
-16-:	568	(disable_sel) ? 
-17-:	568	(advance_sel) ? 
-18-:	571	if (((!en_i) || inv_state))
-19-:	573	if (dis_state)
-20-:	575	if (adv_state)
-21-:	588	((disable_sel | advance_sel)) ? 
-22-:	590	if (((!en_i) || inv_state))
-23-:	592	if ((adv_state || dis_state))
-24-:	614	if ((!op_start_i))
-25-:	629	if (((!en_i) || inv_state))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	Status	Tests
StCtrlReset	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StCtrlReset	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlReset	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlEntropyReseed	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlEntropyReseed	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRandom	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable	T1,T2,T3
StCtrlRandom	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRootKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRootKey	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T42,T43,T44
StCtrlInit	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T13
StCtrlInit	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlInit	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T38,T40,T4
StCtrlInit	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T62
StCtrlInit	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlInit	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T46
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T25,T40
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T46
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T4
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T3,T14,T15
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T13,T51,T6
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T39,T40,T4
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T3,T14,T15
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T3,T13,T14
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T15,T16
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T14,T15
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T14,T17,T18
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T15,T16
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T14,T15
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T13,T14,T17
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T14,T18,T38
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T58,T33,T59
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
StCtrlInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	654	if ((!rst_ni))
-2-:	656	if (update_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	665	case (state_q)

Branches:

-1-	Status	Tests
StCtrlReset StCtrlEntropyReseed StCtrlRandom	Covered	T1,T2,T3
StCtrlRootKey StCtrlInit	Covered	T1,T2,T3
StCtrlCreatorRootKey	Covered	T3,T13,T14
StCtrlOwnerIntKey	Covered	T3,T13,T14
StCtrlOwnerKey	Covered	T3,T14,T15
StCtrlDisabled	Covered	T2,T3,T15
StCtrlWipe	Covered	T13,T14,T17
StCtrlInvalid	Covered	T13,T14,T17
default	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	699	if (op_done_o)
-2-:	703	((|{error_o, fault_o})) ? 
-3-:	704	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	781	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	880	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	27338117	27716	0	0
DataEnDis_A	27050312	27092	0	0
DataEn_A	27050312	6877691	0	0
GeneralLegalCommands_A	28012983	69955	0	0
InitLegalCommands_A	28012983	1472792	0	0
LoadKey_A	27836123	21316088	0	0
OwnerLegalCommands_A	28012983	1612889	0	0
SameErrCnt_A	886	886	0	0
SecCmCFILinear_A	28012983	0	0	4702
StageDisableSel_A	28012983	836785	0	0
u_state_regs_A	28012983	27848107	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27338117	27716	0	0
T1	11109	19	0	0
T2	4461	24	0	0
T3	4989	27	0	0
T13	7613	18	0	0
T14	53712	38	0	0
T15	3864	16	0	0
T16	13112	58	0	0
T17	3976	17	0	0
T18	14724	34	0	0
T19	6173	25	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27050312	27092	0	0
T1	11109	19	0	0
T2	4461	24	0	0
T3	4989	27	0	0
T13	7613	18	0	0
T14	53712	38	0	0
T15	3864	16	0	0
T16	13112	56	0	0
T17	3976	17	0	0
T18	14724	34	0	0
T19	6173	25	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27050312	6877691	0	0
T1	11109	1682	0	0
T2	4461	529	0	0
T3	4989	809	0	0
T13	7613	1602	0	0
T14	53712	22613	0	0
T15	3864	112	0	0
T16	13112	366	0	0
T17	3976	626	0	0
T18	14724	1313	0	0
T19	6173	382	0	0

GeneralLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	69955	0	0
T4	0	2032	0	0
T25	11384	0	0	0
T39	31206	50	0	0
T55	0	25462	0	0
T63	0	974	0	0
T64	0	184	0	0
T65	0	14237	0	0
T66	0	577	0	0
T67	0	21295	0	0
T68	0	4791	0	0
T69	0	186	0	0
T70	4889	0	0	0
T71	65476	0	0	0
T72	4136	0	0	0
T73	11289	0	0	0
T74	119213	0	0	0
T75	46081	0	0	0
T76	5747	0	0	0
T77	5777	0	0	0

InitLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	1472792	0	0
T1	11109	1704	0	0
T2	4461	551	0	0
T3	4989	104	0	0
T13	7613	262	0	0
T14	53712	2842	0	0
T15	3864	16	0	0
T16	13112	110	0	0
T17	3976	227	0	0
T18	14724	97	0	0
T19	6173	67	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27836123	21316088	0	0
T1	11109	5589	0	0
T2	4461	1382	0	0
T3	4989	3062	0	0
T13	7613	2738	0	0
T14	53712	46323	0	0
T15	3864	478	0	0
T16	13112	988	0	0
T17	3976	1108	0	0
T18	14724	3795	0	0
T19	6173	1390	0	0

OwnerLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	1612889	0	0
T3	4989	353	0	0
T7	9659	0	0	0
T13	7613	0	0	0
T14	53712	0	0	0
T15	3864	50	0	0
T16	13112	62	0	0
T17	3976	0	0	0
T18	14724	640	0	0
T19	6173	136	0	0
T58	0	50	0	0
T78	22812	1557	0	0
T79	0	18838	0	0
T80	0	175	0	0
T81	0	4967	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	0	0	4702

StageDisableSel_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	836785	0	0
T1	11109	46	0	0
T2	4461	243	0	0
T3	4989	28	0	0
T13	7613	981	0	0
T14	53712	483	0	0
T15	3864	22	0	0
T16	13112	220	0	0
T17	3976	136	0	0
T18	14724	1064	0	0
T19	6173	18	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	27848107	0	0
T1	11109	11051	0	0
T2	4461	4379	0	0
T3	4989	4924	0	0
T13	7613	7419	0	0
T14	53712	53558	0	0
T15	3864	3789	0	0
T16	13112	12998	0	0
T17	3976	3833	0	0
T18	14724	14582	0	0
T19	6173	6077	0	0