4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 0 | 50 | 0.00 | ||
| V1 | random | keymgr_random | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | keymgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | keymgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 0 | 20 | 0.00 | ||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 155 | 0.00 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 0 | 50 | 0.00 | ||
| V2 | sideload | keymgr_sideload | 0 | 50 | 0.00 | ||
| keymgr_sideload_kmac | 0 | 50 | 0.00 | ||||
| keymgr_sideload_aes | 0 | 50 | 0.00 | ||||
| keymgr_sideload_otbn | 0 | 50 | 0.00 | ||||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 0 | 50 | 0.00 | ||
| V2 | lc_disable | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 0 | 50 | 0.00 | ||
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 0 | 50 | 0.00 | ||
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 0 | 50 | 0.00 | ||
| V2 | stress_all | keymgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | keymgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | keymgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | keymgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| keymgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| keymgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | tl_intg_err | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| keymgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 0 | 50 | 0.00 | ||
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 0 | 165 | 0.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1110 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 6 | 6 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1112 failures:
0.keymgr_smoke.102810741754445013493146244094806851875818420128657151876135074142278502147241
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log
1.keymgr_smoke.40027171763616378468936073777255544558696803537084700347914172425862234874676
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_smoke/latest/run.log
... and 48 more failures.
0.keymgr_sideload.43839519125014078941480801405745746225076364591283129836558306132993037619967
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload/latest/run.log
1.keymgr_sideload.113408480277384071839864976699015283178828037687936261367276570098209700778283
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload/latest/run.log
... and 48 more failures.
0.keymgr_sideload_kmac.46573805220016184777583889916214233981792448690834516668686370670922464065494
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest/run.log
1.keymgr_sideload_kmac.38061856875015002819917864998908674189504180145819380819269329830208043934547
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest/run.log
... and 48 more failures.
0.keymgr_sideload_aes.98530479358921283436950682787548386511269763908214327682389897420036807824529
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log
1.keymgr_sideload_aes.10503201628228822229956791933214846554229140427189521576297797213551855706142
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_aes/latest/run.log
... and 48 more failures.
0.keymgr_sideload_otbn.75135010150866195229218548211079426522701054060195824388480914548285820866829
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest/run.log
1.keymgr_sideload_otbn.76642064587484559182127198755827454540397711731371936982400761837715978373305
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.