Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4245271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

595927

1

T1

142

T2

564

T3

332

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4446671	1			T1	408		T2	606		T3	836
values[0x0]	196534	1			T1	43		T2	200		T3	132
values[0x1]	197993	1			T1	43		T2	228		T3	125

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2887918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1953280

1

T1

229

T2

679

T3

535

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19223	1			T2	1		T3	3		T4	3
valid_sources[0x01]	89338	1			T3	2		T4	3		T14	28
valid_sources[0x02]	18294	1			T2	3		T3	1		T4	8
valid_sources[0x03]	18177	1			T2	6		T3	4		T4	10
valid_sources[0x04]	18900	1			T2	7		T3	5		T4	3
valid_sources[0x05]	27078	1			T2	2		T3	3		T4	2
valid_sources[0x06]	15395	1			T3	4		T4	1		T14	28
valid_sources[0x07]	15083	1			T2	5		T3	4		T4	9
valid_sources[0x08]	15242	1			T2	4		T3	4		T4	2
valid_sources[0x09]	21599	1			T2	4		T3	4		T14	24
valid_sources[0x0a]	16064	1			T2	5		T3	8		T4	1
valid_sources[0x0b]	15660	1			T2	4		T3	5		T4	1
valid_sources[0x0c]	15996	1			T1	19		T2	4		T3	4
valid_sources[0x0d]	15910	1			T2	4		T4	1		T14	32
valid_sources[0x0e]	16682	1			T1	8		T2	2		T3	2
valid_sources[0x0f]	16357	1			T2	6		T3	3		T4	16
valid_sources[0x10]	18414	1			T2	2		T3	6		T4	1
valid_sources[0x11]	20767	1			T2	3		T3	7		T14	26
valid_sources[0x12]	15381	1			T1	2		T2	5		T3	8
valid_sources[0x13]	16208	1			T2	5		T3	4		T4	5
valid_sources[0x14]	19019	1			T2	6		T3	4		T4	4
valid_sources[0x15]	18766	1			T2	5		T3	7		T4	2
valid_sources[0x16]	15705	1			T2	2		T3	8		T4	1
valid_sources[0x17]	19431	1			T2	4		T3	5		T4	5
valid_sources[0x18]	15711	1			T1	6		T2	4		T3	5
valid_sources[0x19]	16690	1			T2	7		T3	8		T14	29
valid_sources[0x1a]	26310	1			T2	8		T3	4		T4	4
valid_sources[0x1b]	15081	1			T2	2		T4	1		T14	38
valid_sources[0x1c]	17072	1			T2	3		T3	2		T14	30
valid_sources[0x1d]	17265	1			T2	3		T3	1		T4	1
valid_sources[0x1e]	15878	1			T2	7		T3	3		T14	31
valid_sources[0x1f]	16369	1			T1	7		T2	4		T3	2
valid_sources[0x20]	18190	1			T1	17		T2	1		T3	6
valid_sources[0x21]	16416	1			T2	2		T3	2		T4	5
valid_sources[0x22]	15366	1			T2	1		T3	7		T4	2
valid_sources[0x23]	15107	1			T2	1		T14	28		T15	5
valid_sources[0x24]	40931	1			T2	5		T3	7		T14	30
valid_sources[0x25]	15545	1			T2	3		T3	10		T4	1
valid_sources[0x26]	15139	1			T2	6		T14	28		T15	8
valid_sources[0x27]	15788	1			T2	7		T3	3		T4	2
valid_sources[0x28]	14890	1			T2	5		T3	4		T4	9
valid_sources[0x29]	15892	1			T2	4		T3	6		T4	1
valid_sources[0x2a]	17706	1			T1	5		T2	6		T3	11
valid_sources[0x2b]	17161	1			T3	4		T14	25		T15	4
valid_sources[0x2c]	15693	1			T2	4		T3	2		T4	2
valid_sources[0x2d]	17982	1			T2	5		T3	8		T14	40
valid_sources[0x2e]	15899	1			T2	7		T3	2		T4	3
valid_sources[0x2f]	14663	1			T2	4		T3	3		T4	1
valid_sources[0x30]	21339	1			T2	4		T3	4		T4	3
valid_sources[0x31]	16151	1			T1	1		T2	3		T3	4
valid_sources[0x32]	15293	1			T2	4		T3	3		T14	33
valid_sources[0x33]	15359	1			T1	1		T2	6		T3	7
valid_sources[0x34]	15804	1			T2	3		T3	2		T14	32
valid_sources[0x35]	15882	1			T1	43		T2	1		T3	3
valid_sources[0x36]	15225	1			T1	4		T2	1		T3	7
valid_sources[0x37]	15901	1			T1	16		T2	8		T3	3
valid_sources[0x38]	14982	1			T2	5		T3	5		T4	1
valid_sources[0x39]	15316	1			T2	4		T3	4		T4	7
valid_sources[0x3a]	15622	1			T2	4		T3	7		T4	5
valid_sources[0x3b]	14713	1			T2	3		T3	4		T14	32
valid_sources[0x3c]	18342	1			T2	1		T3	5		T14	26
valid_sources[0x3d]	15732	1			T2	1		T3	8		T14	30
valid_sources[0x3e]	16911	1			T1	4		T2	4		T3	12
valid_sources[0x3f]	17228	1			T2	3		T3	1		T4	3
valid_sources[0x40]	14398	1			T1	1		T2	8		T3	6
valid_sources[0x41]	31861	1			T2	3		T3	4		T4	5
valid_sources[0x42]	15941	1			T2	4		T3	2		T14	39
valid_sources[0x43]	15244	1			T2	5		T3	6		T14	27
valid_sources[0x44]	90412	1			T2	4		T3	4		T4	2
valid_sources[0x45]	15224	1			T2	5		T3	6		T4	4
valid_sources[0x46]	15092	1			T2	1		T3	5		T4	5
valid_sources[0x47]	18153	1			T2	4		T3	4		T14	29
valid_sources[0x48]	45102	1			T2	3		T3	3		T4	3
valid_sources[0x49]	34626	1			T1	12		T2	6		T3	2
valid_sources[0x4a]	38714	1			T2	4		T3	3		T4	9
valid_sources[0x4b]	19646	1			T2	3		T3	4		T14	27
valid_sources[0x4c]	14854	1			T2	4		T3	3		T14	25
valid_sources[0x4d]	18378	1			T2	6		T3	4		T4	1
valid_sources[0x4e]	16860	1			T2	3		T3	7		T14	29
valid_sources[0x4f]	82389	1			T2	4		T3	4		T14	32
valid_sources[0x50]	19911	1			T2	4		T3	1		T14	24
valid_sources[0x51]	16698	1			T1	1		T2	2		T3	4
valid_sources[0x52]	18202	1			T2	2		T3	4		T4	3
valid_sources[0x53]	16581	1			T1	10		T2	4		T3	2
valid_sources[0x54]	17720	1			T2	4		T3	2		T4	2
valid_sources[0x55]	16722	1			T2	7		T3	1		T14	27
valid_sources[0x56]	15510	1			T2	3		T3	5		T4	1
valid_sources[0x57]	18753	1			T2	3		T3	2		T4	2
valid_sources[0x58]	17160	1			T2	5		T3	5		T14	28
valid_sources[0x59]	15901	1			T2	3		T3	7		T4	4
valid_sources[0x5a]	14708	1			T2	1		T3	3		T4	1
valid_sources[0x5b]	17151	1			T1	6		T2	5		T3	5
valid_sources[0x5c]	44159	1			T2	5		T3	1		T14	24
valid_sources[0x5d]	33604	1			T1	2		T2	4		T3	3
valid_sources[0x5e]	16282	1			T2	6		T3	4		T4	3
valid_sources[0x5f]	15447	1			T2	7		T3	6		T14	36
valid_sources[0x60]	15934	1			T2	4		T3	2		T4	2
valid_sources[0x61]	15219	1			T2	3		T4	3		T14	35
valid_sources[0x62]	15031	1			T2	5		T3	3		T4	5
valid_sources[0x63]	15747	1			T1	20		T3	2		T4	5
valid_sources[0x64]	14922	1			T2	7		T3	8		T4	2
valid_sources[0x65]	23200	1			T1	2		T2	2		T3	5
valid_sources[0x66]	14776	1			T2	3		T3	8		T4	2
valid_sources[0x67]	16419	1			T2	4		T3	2		T4	3
valid_sources[0x68]	25333	1			T2	2		T3	1		T4	2
valid_sources[0x69]	17175	1			T1	5		T2	2		T3	3
valid_sources[0x6a]	31911	1			T2	8		T3	14		T4	2
valid_sources[0x6b]	15587	1			T2	8		T3	9		T4	1
valid_sources[0x6c]	25577	1			T2	7		T3	5		T4	4
valid_sources[0x6d]	14689	1			T2	7		T3	3		T14	29
valid_sources[0x6e]	15568	1			T2	1		T3	6		T14	38
valid_sources[0x6f]	14622	1			T2	6		T3	5		T4	1
valid_sources[0x70]	16811	1			T1	2		T2	1		T3	4
valid_sources[0x71]	14700	1			T2	2		T3	2		T14	33
valid_sources[0x72]	15099	1			T2	5		T3	5		T4	2
valid_sources[0x73]	16655	1			T2	4		T3	1		T4	5
valid_sources[0x74]	16159	1			T2	3		T3	6		T4	3
valid_sources[0x75]	18334	1			T2	2		T3	3		T4	8
valid_sources[0x76]	16085	1			T2	9		T3	6		T4	1
valid_sources[0x77]	15157	1			T1	7		T2	5		T3	1
valid_sources[0x78]	24650	1			T2	5		T3	1		T14	27
valid_sources[0x79]	15446	1			T1	2		T2	2		T3	1
valid_sources[0x7a]	16449	1			T2	3		T3	1		T14	29
valid_sources[0x7b]	18113	1			T2	3		T3	2		T4	4
valid_sources[0x7c]	53880	1			T1	1		T2	3		T4	3
valid_sources[0x7d]	29153	1			T2	3		T3	3		T14	31
valid_sources[0x7e]	16562	1			T1	4		T2	3		T3	17
valid_sources[0x7f]	16156	1			T1	2		T2	4		T3	2
valid_sources[0x80]	19094	1			T1	22		T2	5		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

329158

1

T1

120

T2

279

T3

155

values[0x0]

all_enables

biggest_size

140801

1

T1

18

T2

151

T3

96

values[0x1]

all_enables

biggest_size

125968

1

T1

4

T2

134

T3

81