Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4271623	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

580897

1

T1

345

T2

516

T3

297

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4461540	1			T1	346		T2	1087		T3	784
values[0x0]	194762	1			T1	125		T2	159		T3	94
values[0x1]	196218	1			T1	131		T2	132		T3	90

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2906432	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1946088

1

T1

404

T2

719

T3

479

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15660	1			T2	5		T3	4		T5	2
valid_sources[0x01]	14622	1			T2	12		T3	10		T5	3
valid_sources[0x02]	18642	1			T1	1		T2	5		T3	3
valid_sources[0x03]	14691	1			T2	12		T3	5		T4	31
valid_sources[0x04]	16047	1			T1	62		T2	4		T3	2
valid_sources[0x05]	14925	1			T2	11		T3	1		T5	8
valid_sources[0x06]	15933	1			T2	4		T3	5		T5	5
valid_sources[0x07]	17619	1			T1	1		T3	3		T4	34
valid_sources[0x08]	14210	1			T2	8		T3	1		T4	20
valid_sources[0x09]	20471	1			T2	20		T3	1		T5	2
valid_sources[0x0a]	15207	1			T3	1		T5	2		T6	4
valid_sources[0x0b]	15547	1			T2	8		T3	4		T5	4
valid_sources[0x0c]	15530	1			T2	5		T3	7		T6	6
valid_sources[0x0d]	16911	1			T3	1		T4	4		T5	3
valid_sources[0x0e]	16940	1			T2	4		T3	3		T5	2
valid_sources[0x0f]	17015	1			T2	2		T3	3		T4	13
valid_sources[0x10]	15464	1			T2	3		T3	15		T5	2
valid_sources[0x11]	17173	1			T2	10		T3	12		T5	5
valid_sources[0x12]	15477	1			T2	6		T3	6		T5	4
valid_sources[0x13]	20402	1			T2	4		T3	6		T6	2
valid_sources[0x14]	25139	1			T2	14		T3	4		T5	3
valid_sources[0x15]	17397	1			T2	2		T3	7		T5	4
valid_sources[0x16]	15293	1			T2	12		T3	3		T5	2
valid_sources[0x17]	19538	1			T2	11		T3	7		T5	4
valid_sources[0x18]	15514	1			T2	4		T3	6		T4	17
valid_sources[0x19]	15945	1			T2	9		T3	2		T5	7
valid_sources[0x1a]	14622	1			T2	2		T3	8		T5	2
valid_sources[0x1b]	15628	1			T2	3		T3	8		T5	3
valid_sources[0x1c]	14484	1			T2	7		T3	1		T5	1
valid_sources[0x1d]	16085	1			T2	1		T3	2		T5	4
valid_sources[0x1e]	16258	1			T2	3		T4	1		T5	3
valid_sources[0x1f]	21107	1			T2	3		T3	14		T5	3
valid_sources[0x20]	16800	1			T2	4		T3	1		T4	19
valid_sources[0x21]	21792	1			T2	12		T3	9		T4	2
valid_sources[0x22]	25192	1			T2	7		T4	20		T5	3
valid_sources[0x23]	16093	1			T2	8		T3	5		T5	1
valid_sources[0x24]	15236	1			T2	5		T3	3		T5	3
valid_sources[0x25]	15497	1			T2	11		T3	7		T5	2
valid_sources[0x26]	15585	1			T2	14		T3	1		T4	5
valid_sources[0x27]	15449	1			T2	9		T3	1		T5	5
valid_sources[0x28]	18663	1			T5	1		T6	2		T14	8
valid_sources[0x29]	15709	1			T2	3		T3	11		T6	4
valid_sources[0x2a]	14809	1			T2	8		T3	4		T4	12
valid_sources[0x2b]	20665	1			T2	10		T3	4		T4	3
valid_sources[0x2c]	16791	1			T1	536		T2	19		T3	4
valid_sources[0x2d]	14238	1			T2	13		T3	5		T5	1
valid_sources[0x2e]	33064	1			T2	1		T3	10		T5	1
valid_sources[0x2f]	15528	1			T2	1		T3	3		T4	16
valid_sources[0x30]	16282	1			T2	2		T3	1		T5	7
valid_sources[0x31]	30505	1			T2	5		T3	3		T4	11
valid_sources[0x32]	28069	1			T2	9		T3	2		T5	3
valid_sources[0x33]	15233	1			T2	4		T3	7		T5	5
valid_sources[0x34]	16805	1			T2	9		T3	2		T5	5
valid_sources[0x35]	15238	1			T4	12		T5	3		T6	3
valid_sources[0x36]	14696	1			T2	2		T3	1		T6	1
valid_sources[0x37]	14831	1			T2	5		T3	1		T5	1
valid_sources[0x38]	28434	1			T2	7		T3	2		T6	4
valid_sources[0x39]	15291	1			T3	4		T4	21		T5	1
valid_sources[0x3a]	18596	1			T2	4		T3	7		T6	1
valid_sources[0x3b]	16104	1			T2	2		T3	6		T5	4
valid_sources[0x3c]	15304	1			T2	5		T3	4		T4	27
valid_sources[0x3d]	16084	1			T2	5		T3	5		T5	2
valid_sources[0x3e]	15846	1			T2	10		T3	1		T5	12
valid_sources[0x3f]	15443	1			T2	8		T3	5		T4	15
valid_sources[0x40]	15607	1			T2	2		T3	2		T6	3
valid_sources[0x41]	15032	1			T2	10		T3	3		T5	3
valid_sources[0x42]	18916	1			T2	3		T3	5		T6	3
valid_sources[0x43]	22397	1			T2	2		T3	2		T5	3
valid_sources[0x44]	17901	1			T2	1		T3	3		T5	4
valid_sources[0x45]	16831	1			T3	2		T5	7		T6	3
valid_sources[0x46]	36806	1			T2	12		T3	6		T5	10
valid_sources[0x47]	15719	1			T2	9		T3	1		T5	2
valid_sources[0x48]	15405	1			T2	7		T3	6		T5	7
valid_sources[0x49]	15386	1			T2	6		T5	1		T6	1
valid_sources[0x4a]	19111	1			T2	8		T3	12		T5	8
valid_sources[0x4b]	32374	1			T2	4		T3	3		T4	80
valid_sources[0x4c]	32820	1			T2	6		T3	3		T4	14
valid_sources[0x4d]	16463	1			T2	8		T3	5		T5	4
valid_sources[0x4e]	33437	1			T2	5		T3	1		T5	1
valid_sources[0x4f]	18091	1			T2	1		T3	2		T5	3
valid_sources[0x50]	14859	1			T2	6		T3	2		T4	5
valid_sources[0x51]	15381	1			T2	3		T3	1		T4	7
valid_sources[0x52]	17170	1			T2	3		T4	4		T5	4
valid_sources[0x53]	23542	1			T4	4		T15	18		T16	6
valid_sources[0x54]	16501	1			T2	9		T3	4		T4	16
valid_sources[0x55]	14782	1			T2	9		T3	1		T5	4
valid_sources[0x56]	15149	1			T1	1		T2	4		T3	4
valid_sources[0x57]	14870	1			T2	11		T5	3		T6	5
valid_sources[0x58]	14777	1			T2	1		T3	3		T6	2
valid_sources[0x59]	15453	1			T3	2		T4	10		T6	3
valid_sources[0x5a]	27007	1			T2	8		T3	5		T5	10
valid_sources[0x5b]	17906	1			T2	7		T3	6		T4	2
valid_sources[0x5c]	19348	1			T2	3		T3	4		T5	2
valid_sources[0x5d]	15490	1			T2	5		T3	3		T4	2
valid_sources[0x5e]	19008	1			T2	2		T3	4		T5	1
valid_sources[0x5f]	15356	1			T2	10		T3	9		T4	20
valid_sources[0x60]	15461	1			T2	2		T3	7		T4	17
valid_sources[0x61]	15481	1			T2	6		T3	5		T6	8
valid_sources[0x62]	17130	1			T3	1		T4	38		T5	1
valid_sources[0x63]	15045	1			T2	4		T3	6		T5	2
valid_sources[0x64]	19406	1			T2	4		T3	10		T4	19
valid_sources[0x65]	16282	1			T2	6		T3	5		T6	3
valid_sources[0x66]	17737	1			T2	6		T3	1		T5	1
valid_sources[0x67]	17882	1			T2	16		T5	3		T6	1
valid_sources[0x68]	25895	1			T2	4		T3	4		T5	1
valid_sources[0x69]	20825	1			T3	2		T5	3		T6	1
valid_sources[0x6a]	15652	1			T2	5		T3	6		T5	2
valid_sources[0x6b]	19420	1			T2	7		T3	8		T5	3
valid_sources[0x6c]	16016	1			T2	2		T3	4		T5	4
valid_sources[0x6d]	15161	1			T2	1		T3	3		T5	7
valid_sources[0x6e]	20838	1			T2	10		T3	1		T5	7
valid_sources[0x6f]	17659	1			T2	3		T3	1		T5	13
valid_sources[0x70]	16715	1			T2	1		T3	6		T14	14
valid_sources[0x71]	14605	1			T2	1		T5	5		T6	5
valid_sources[0x72]	16281	1			T2	8		T3	2		T4	27
valid_sources[0x73]	14902	1			T2	3		T3	7		T5	6
valid_sources[0x74]	15200	1			T2	10		T3	13		T6	4
valid_sources[0x75]	15053	1			T1	1		T2	12		T6	4
valid_sources[0x76]	19119	1			T3	3		T5	5		T6	1
valid_sources[0x77]	25448	1			T3	4		T5	2		T6	4
valid_sources[0x78]	25084	1			T2	13		T4	6		T5	1
valid_sources[0x79]	15246	1			T2	1		T3	2		T5	3
valid_sources[0x7a]	24710	1			T2	8		T5	7		T6	2
valid_sources[0x7b]	14939	1			T2	6		T3	6		T5	1
valid_sources[0x7c]	16532	1			T2	4		T3	2		T4	12
valid_sources[0x7d]	18203	1			T2	5		T3	5		T5	1
valid_sources[0x7e]	16422	1			T2	4		T3	3		T5	5
valid_sources[0x7f]	16848	1			T2	3		T5	2		T6	1
valid_sources[0x80]	40927	1			T2	1		T3	2		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

316831

1

T1

158

T2

352

T3

170

values[0x0]

all_enables

biggest_size

139087

1

T1

93

T2

96

T3

70

values[0x1]

all_enables

biggest_size

124979

1

T1

94

T2

68

T3

57